From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Stephane Eranian <eranian@google.com>
Cc: Lin Ming <ming.m.lin@intel.com>, Ingo Molnar <mingo@elte.hu>,
Andi Kleen <andi@firstfloor.org>,
lkml <linux-kernel@vger.kernel.org>, paulus <paulus@samba.org>
Subject: Re: [PATCH 2/7] perf-events: Add support for supplementary event registers v4
Date: Thu, 13 Jan 2011 18:41:05 +0100 [thread overview]
Message-ID: <1294940465.30950.8.camel@laptop> (raw)
In-Reply-To: <AANLkTik9adcY_pH52c_Y0iRjitDKZOu5zyPusfjycuiH@mail.gmail.com>
On Thu, 2011-01-13 at 18:31 +0100, Stephane Eranian wrote:
> In fact, given that the Sandy Bridge PMU spec is now available, we
> have a first example of this (see Vol3b figure 30.29). OFFCORE_RESPONSE
> needs 38 bits. So, instead of having NHM/WSM use attr->config and SNB
> use another field, I think it would make sense to have that in a new u64 field
> for all processors. Despite the fact that OFFCORE_RESPONSE remains
> a model-specific feature, I think it would help user tools and libraries if we
> were to use a dedicated field.
Paul, iirc you talked about a u64 perf_event_attr::config2 way back, are
there any ppc features that want this too?
next prev parent reply other threads:[~2011-01-13 17:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-27 15:36 [PATCH 2/7] perf-events: Add support for supplementary event registers v4 Lin Ming
2011-01-13 17:31 ` Stephane Eranian
2011-01-13 17:41 ` Peter Zijlstra [this message]
2011-01-13 20:41 ` Andi Kleen
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