Re: [3/4] OMAP: DSS2: Adding macro for DISPC_DIVISOR register

[Tomi Valkeinen <tomi.valkeinen@ti.com>]

On Thu, 2011-02-03 at 14:09 +0000, Raghuveer Murthy wrote:
> Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and
> DISPC_DIVISOR2. OMAP4 supports all the above 3 registers.
> 
> DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through
> DISPC_DIVISORo(ch) macro
> 
> Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
> 
> ---
> drivers/video/omap2/dss/dispc.c |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index e52a413..6225d12 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -132,6 +132,17 @@ struct dispc_reg { u16 idx; };
>  
>  #define DISPC_VID_PRELOAD(n)		DISPC_REG(0x230 + (n)*0x04)
>  
> +/*
> + * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
> + * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
> + * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
> + * of LCD1 (primary) and LCD2 (secondary) displays.
> + *
> + * To derive pixel clocks for Primary and Secondary LCD channels, configure the
> + * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
> + * DISPC_DIVISORo(ch).
> + */
> +#define DISPC_DIVISOR			DISPC_REG(0x0804)
>  
>  #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
>  					 DISPC_IRQ_OCP_ERR | \

See my comment about comments in previous mail.

I think you should merge this and the next patch. There's not much point
in adding a single line define, which is not used (yet).

How about the debug output from debug/omapdss/clk file? Does it print
sensible things on OMAP4 after these patches?

 Tomi