Re: [PATCH] invalid instructions in kernel mode

[Dan Malek <dan@embeddededge.com>]

On Mar 31, 2005, at 2:17 PM, Fillod Stephane wrote:

> What I don't understand, is how the FP load/store operations
> in misc.S can "work" on a system with no FPU and *no* math-emu?

What should happen is to follow the example used by 8xx for
many years.  As I said, when math emulation is disabled, there is
still code that will emulate the load/store FP instructions.  These
instructions are used in may places even if user applications
are compiled without any FP usage.

> Many years? Allow me to doubt it's really used :).

I wrote it in 1998 for the 8xx.  I thought 4xx and e500 used the
same model.  If they don't, they should.

> Though, it does work for 8xx thanks to Soft_emulate_8xx, but doesn't
> for other FPU-less cores when CONFIG_MATH_EMULATION is disabled.

Well, then that should get fixed.

> So here is another patch,

The only patch I'm interested in is making the 4xx and e500 follow the
same path as 8xx.  All of the non-FP cores should work the same way.
The e500 is a special case because it doesn't have a classic FPU but
rather can utilize the SPE for floating point.  Put some thought into 
that.

Thanks.


	-- Dan