Re: [PATCH 1/1] nv50: improve nv50_pm_clock_get()

[Ben Skeggs <skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

On Fri, 2011-03-18 at 01:15 +0000, Emil Velikov wrote:
> On some cards the memory and/or shader pll can be switched off/disabled
> Check and return the linked/standart clock
> 
> Signed-off-by: Emil Velikov <emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/gpu/drm/nouveau/nv50_pm.c |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
> index 7dbb305..c01a64f 100644
> --- a/drivers/gpu/drm/nouveau/nv50_pm.c
> +++ b/drivers/gpu/drm/nouveau/nv50_pm.c
> @@ -47,6 +47,19 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id)
>  
>  	reg0 = nv_rd32(dev, pll.reg + 0);
>  	reg1 = nv_rd32(dev, pll.reg + 4);
> +
> +	if ((reg0 & 0x80000000) == 0) {
> +		if (id == PLL_SHADER) {
> +			NV_INFO(dev, "Shader PLL appears to be OFF\n");
> +			ret = nv50_pm_clock_get(dev, PLL_CORE);
> +			if (ret > 0)
> +				return ret*2;
This seems somewhat OK, from what I recall seeing.  Have you seen any
definite evidence to suggest that the shaders actually run at double the
core clock if the PLL is "off"?

> +		} else if (id == PLL_MEMORY) {
> +			NV_INFO(dev, "Memory PLL appears to be OFF\n");
> +			return 100*1000;
This, is more dubious.  Are you trying to indicate that it's running at
the reference clock?  Or always at a fixed 100MHz?

Ben.
> +		}
> +	}
> +
>  	P = (reg0 & 0x00070000) >> 16;
>  	N = (reg1 & 0x0000ff00) >> 8;
>  	M = (reg1 & 0x000000ff);