[U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101

[Macpaul Lin <macpaul@andestech.com>]

Add header file of device offset support for SoC ag101.

SoC ag101 is the first chip using NDS32 N1213 cpu core.

Note:
   Ag101 is actually use ftsdmc021 instead of ftsdmc020
   as dram controller, which is probably wrong in the datasheet.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
 arch/nds32/include/asm/arch-ag101/ag101.h |   68 +++++++++++++++++++++++++++++
 1 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h

diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE		0x90100000	/* AHB Controller */
+#define CONFIG_FTSMC020_BASE		0x90200000	/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE		0x90300000	/* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000	/* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000	/* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE		0x90600000	/* LCD Controller */
+#define CONFIG_RESERVED_01_BASE		0x90700000	/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000	/* Reserved */
+#define CONFIG_FTMAC100_BASE		0x90900000	/* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000	/* External USB host */
+#define CONFIG_USB_DEV_BASE		0x90B00000	/* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000	/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE		0x90D00000	/* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000	/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000	/* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000	/* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC	/* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE		0x98100000	/* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE	0x98300000	/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE		0x98400000	/* Counter/Timers */
+#define CONFIG_FTWDT010_BASE		0x98500000	/* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE		0x98600000	/* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE		0x98700000	/* GPIO */
+#define CONFIG_FTINTC010_BASE		0x98800000	/* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE		0x98A00000	/* I2C */
+#define CONFIG_RESERVED_04_BASE		0x98C00000	/* Reserved */
+#define CONFIG_FTCFC010_BASE		0x98D00000	/* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE		0x98E00000	/* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE		0x99400000	/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE	0x99600000	/* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE	0x98200000	/* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000	/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE		0x98900000	/* IrDA */
+#define CONFIG_PMW_BASE			0x99100000	/* PWM - Pulse Width Modulator Controller */
+
+#endif	/* __AG101_H */
-- 
1.7.3.5