From: Lin Ming <ming.m.lin@intel.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu
Date: Tue, 05 Jul 2011 20:48:39 +0800 [thread overview]
Message-ID: <1309870119.2381.6.camel@localhost> (raw)
In-Reply-To: <1309864954.3282.61.camel@twins>
On Tue, 2011-07-05 at 19:22 +0800, Peter Zijlstra wrote:
> On Mon, 2011-07-04 at 23:57 +0200, Andi Kleen wrote:
> > > > There are no NMIs without sampling, so at least the comment seems bogus.
> > > > Perhaps the code could be a bit simplified now without atomics.
> > >
> > > I'm not sure if uncore PMU interrupt need to be enabled for counting
> > > only. What do you think?
> >
> > Only for overflow handling to accumulate into a larger counter, but it doesn't
> > need to be an NMI for that.
>
> Uncore is hooked into the regular PMI, and since we wire that to the NMI
> the uncore will always be NMI too.
>
> > But it's not strictly required I would say,
> > 44(?) bits are probably enough for near all use cases.
>
> 44bits is in the hours range for pure cycle counts, which is so-so. I
> bet you're going to be very annoyed when you find your counters are
> wrecked after your 5 hour test run finishes.
I'll add the interrupt handling code back.
next prev parent reply other threads:[~2011-07-05 12:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-30 8:09 [PATCH 0/4] perf: Intel uncore pmu counting support Lin Ming
2011-06-30 8:09 ` [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu Lin Ming
2011-06-30 14:08 ` Peter Zijlstra
2011-07-01 6:05 ` Lin Ming
2011-06-30 16:58 ` Andi Kleen
2011-07-04 6:39 ` Lin Ming
2011-07-04 8:38 ` Peter Zijlstra
2011-07-04 21:57 ` Andi Kleen
2011-07-05 11:22 ` Peter Zijlstra
2011-07-05 12:48 ` Lin Ming [this message]
2011-07-05 12:56 ` Peter Zijlstra
2011-07-05 13:13 ` Lin Ming
2011-07-05 16:01 ` Andi Kleen
2011-07-06 9:35 ` Ingo Molnar
2011-06-30 8:09 ` [PATCH 2/4] perf, x86: Add Intel SandyBridge " Lin Ming
2011-06-30 22:09 ` Peter Zijlstra
2011-06-30 8:09 ` [PATCH 3/4] perf: Remove perf_event_attr::type check Lin Ming
2011-07-21 19:31 ` [tip:perf/core] " tip-bot for Lin Ming
2011-06-30 8:09 ` [PATCH 4/4] perf tool: Get PMU type id from sysfs Lin Ming
2011-06-30 12:10 ` [PATCH 0/4] perf: Intel uncore pmu counting support Stephane Eranian
2011-06-30 14:10 ` Peter Zijlstra
2011-06-30 16:27 ` Stephane Eranian
2011-07-01 3:17 ` Lin Ming
2011-07-01 10:49 ` Stephane Eranian
2011-07-01 12:23 ` Stephane Eranian
2011-07-01 12:28 ` Stephane Eranian
2011-07-04 6:03 ` Lin Ming
2011-07-01 5:49 ` Lin Ming
2011-07-01 11:08 ` Ingo Molnar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1309870119.2381.6.camel@localhost \
--to=ming.m.lin@intel.com \
--cc=a.p.zijlstra@chello.nl \
--cc=acme@ghostprotocols.net \
--cc=andi@firstfloor.org \
--cc=eranian@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.