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Subject: Re: [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Lin Ming <ming.m.lin@intel.com>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@elte.hu>,
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Date: Tue, 05 Jul 2011 14:56:02 +0200
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On Tue, 2011-07-05 at 20:48 +0800, Lin Ming wrote:
> On Tue, 2011-07-05 at 19:22 +0800, Peter Zijlstra wrote:
> > On Mon, 2011-07-04 at 23:57 +0200, Andi Kleen wrote:
> > > > > There are no NMIs without sampling, so at least the comment seems bogus.
> > > > > Perhaps the code could be a bit simplified now without atomics.
> > > > 
> > > > I'm not sure if uncore PMU interrupt need to be enabled for counting
> > > > only. What do you think?
> > > 
> > > Only for overflow handling to accumulate into a larger counter, but it doesn't 
> > > need to be an NMI for that.
> > 
> > Uncore is hooked into the regular PMI, and since we wire that to the NMI
> > the uncore will always be NMI too.
> > 
> > >   But it's not strictly required I would say, 
> > > 44(?) bits are probably enough for near all use cases.
> > 
> > 44bits is in the hours range for pure cycle counts, which is so-so. I
> > bet you're going to be very annoyed when you find your counters are
> > wrecked after your 5 hour test run finishes.
> 
> I'll add the interrupt handling code back.

Does it work? The problem was with the hardware being iffy.