Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Krzysztof Kozlowski <krzk@kernel.org>]

On 20/06/2025 10:26, Hongxing Zhu wrote:
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 2025年6月20日 15:53
>> To: Hongxing Zhu <hongxing.zhu@nxp.com>
>> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
>> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
>> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
>> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
>> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
>> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
>> imx@lists.linux.dev; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
>> mode support
>>
>> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
>>> On i.MX, the PCIe reference clock might come from either internal
>>> system PLL or external clock source.
>>> Add the external reference clock source for reference clock.
>>>
>>> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
>>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>>> ---
>>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> index ca5f2970f217..c472a5daae6e 100644
>>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> @@ -219,7 +219,12 @@ allOf:
>>>              - const: pcie_bus
>>>              - const: pcie_phy
>>>              - const: pcie_aux
>>> -            - const: ref
>>> +            - description: PCIe reference clock.
>>> +              oneOf:
>>> +                - description: The controller might be configured
>> clocking
>>> +                    coming in from either an internal system PLL or
>> an
>>> +                    external clock source.
>>> +                  enum: [ref, gio]
>>
>> Internal like within PCIe or coming from other SoC block? What does "gio"
>> mean?
> Internal means that the PCIe reference clock is coming from other
>  internal SoC block, such as system PLL. "gio" is on behalf that the
> reference clock comes form external crystal oscillator.

Then what does "ref" mean, if gio is the clock supplied externally? We
talk here about signals coming to this chip, regardless how they are
generated.


Best regards,
Krzysztof