From mboxrd@z Thu Jan 1 00:00:00 1970 From: George Dunlap Subject: Re: AMD IOMMU intremap tables and IOAPICs Date: Tue, 6 Sep 2011 17:03:41 +0100 Message-ID: <1315325021.11099.2.camel@elijah> References: <4E664228.5070606@citrix.com> <20110906160612.GA12835@ocelot.phlegethon.org> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20110906160612.GA12835@ocelot.phlegethon.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Tim Deegan Cc: George Dunlap , Andrew Cooper , "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org On Tue, 2011-09-06 at 17:06 +0100, Tim Deegan wrote: > At 16:54 +0100 on 06 Sep (1315328056), Andrew Cooper wrote: > > On 06/09/11 16:47, George Dunlap wrote: > > > Wei, > > > > > > Quick question: Am I reading the code correctly, that even with > > > per-device interrupt remap tables, that GSIs are accounted to the > > > intremap table of the corresponding IOAPIC, presumably because the > > > IOMMU sees interrupts generated as GSIs as coming from the IOAPIC? In > > > that case, then we need all devices sharing the same IOAPIC must not > > > have any vector collisions. Is that correct? > > > > Based on the ICH10 IO-APIC documentation with respect to auto EOIs, we > > cant have any two IRQs across any IO-APICs sharing a vector, > > irrespective of IOMMU or not. (Because the EOI'ing an IO-APIC entry > > only takes account of vector and not destination) > > If this is the case, is there any point in having per-CPU IDTs? > Or per-device remapping tables? Yes, for devices that use MSIs, at least. -George