* [Qemu-devel] [PATCH 1/2] target-xtensa: implement MAC16 option
2011-10-10 2:25 [Qemu-devel] [PATCH 0/2] target-xtensa: implement MAC16 option and unit tests for it Max Filippov
@ 2011-10-10 2:25 ` Max Filippov
2011-10-10 2:25 ` [Qemu-devel] [PATCH 2/2] target-xtensa: add MAC16 unit tests Max Filippov
2011-10-15 21:36 ` [Qemu-devel] [PATCH 0/2] target-xtensa: implement MAC16 option and unit tests for it Blue Swirl
2 siblings, 0 replies; 4+ messages in thread
From: Max Filippov @ 2011-10-10 2:25 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
See ISA, 4.3.7 for the details.
- add ACC and MR special registers;
- implement MAC16 and all inner MAC* opcode groups.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/cpu.h | 3 +
target-xtensa/translate.c | 135 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 137 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 966f515..b43e565 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -113,6 +113,9 @@ enum {
BR = 4,
LITBASE = 5,
SCOMPARE1 = 12,
+ ACCLO = 16,
+ ACCHI = 17,
+ MR = 32,
WINDOW_BASE = 72,
WINDOW_START = 73,
PTEVADDR = 83,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 93a807e..70bea62 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -79,6 +79,12 @@ static const char * const sregnames[256] = {
[BR] = "BR",
[LITBASE] = "LITBASE",
[SCOMPARE1] = "SCOMPARE1",
+ [ACCLO] = "ACCLO",
+ [ACCHI] = "ACCHI",
+ [MR] = "MR0",
+ [MR + 1] = "MR1",
+ [MR + 2] = "MR2",
+ [MR + 3] = "MR3",
[WINDOW_BASE] = "WINDOW_BASE",
[WINDOW_START] = "WINDOW_START",
[PTEVADDR] = "PTEVADDR",
@@ -447,6 +453,11 @@ static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
gen_jumpi_check_loop_end(dc, -1);
}
+static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+{
+ tcg_gen_ext8s_i32(cpu_SR[sr], s);
+}
+
static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
gen_helper_wsr_windowbase(v);
@@ -544,6 +555,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
[SAR] = gen_wsr_sar,
[BR] = gen_wsr_br,
[LITBASE] = gen_wsr_litbase,
+ [ACCHI] = gen_wsr_acchi,
[WINDOW_BASE] = gen_wsr_windowbase,
[WINDOW_START] = gen_wsr_windowstart,
[PTEVADDR] = gen_wsr_ptevaddr,
@@ -628,6 +640,18 @@ static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
}
+static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
+{
+ TCGv_i32 m = tcg_temp_new_i32();
+
+ if (hi) {
+ (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
+ } else {
+ (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
+ }
+ return m;
+}
+
static void disas_xtensa_insn(DisasContext *dc)
{
#define HAS_OPTION_BITS(opt) do { \
@@ -663,6 +687,9 @@ static void disas_xtensa_insn(DisasContext *dc)
#define RRR_S (((b1) & 0xf))
#define RRR_T (((b0) & 0xf0) >> 4)
#endif
+#define RRR_X ((RRR_R & 0x4) >> 2)
+#define RRR_Y ((RRR_T & 0x4) >> 2)
+#define RRR_W (RRR_R & 0x3)
#define RRRN_R RRR_R
#define RRRN_S RRR_S
@@ -1935,7 +1962,113 @@ static void disas_xtensa_insn(DisasContext *dc)
case 4: /*MAC16d*/
HAS_OPTION(XTENSA_OPTION_MAC16);
- TBD();
+ {
+ enum {
+ MAC16_UMUL = 0x0,
+ MAC16_MUL = 0x4,
+ MAC16_MULA = 0x8,
+ MAC16_MULS = 0xc,
+ MAC16_NONE = 0xf,
+ } op = OP1 & 0xc;
+ bool is_m1_sr = (OP2 & 0x3) == 2;
+ bool is_m2_sr = (OP2 & 0xc) == 0;
+ uint32_t ld_offset = 0;
+
+ if (OP2 > 9) {
+ RESERVED();
+ }
+
+ switch (OP2 & 2) {
+ case 0: /*MACI?/MACC?*/
+ is_m1_sr = true;
+ ld_offset = (OP2 & 1) ? -4 : 4;
+
+ if (OP2 >= 8) { /*MACI/MACC*/
+ if (OP1 == 0) { /*LDINC/LDDEC*/
+ op = MAC16_NONE;
+ } else {
+ RESERVED();
+ }
+ } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
+ RESERVED();
+ }
+ break;
+
+ case 2: /*MACD?/MACA?*/
+ if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
+ RESERVED();
+ }
+ break;
+ }
+
+ if (op != MAC16_NONE) {
+ if (!is_m1_sr) {
+ gen_window_check1(dc, RRR_S);
+ }
+ if (!is_m2_sr) {
+ gen_window_check1(dc, RRR_T);
+ }
+ }
+
+ {
+ TCGv_i32 vaddr = tcg_temp_new_i32();
+ TCGv_i32 mem32 = tcg_temp_new_i32();
+
+ if (ld_offset) {
+ gen_window_check1(dc, RRR_S);
+ tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
+ gen_load_store_alignment(dc, 2, vaddr, false);
+ tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
+ }
+ if (op != MAC16_NONE) {
+ TCGv_i32 m1 = gen_mac16_m(
+ is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
+ OP1 & 1, op == MAC16_UMUL);
+ TCGv_i32 m2 = gen_mac16_m(
+ is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
+ OP1 & 2, op == MAC16_UMUL);
+
+ if (op == MAC16_MUL || op == MAC16_UMUL) {
+ tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
+ if (op == MAC16_UMUL) {
+ tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
+ } else {
+ tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
+ }
+ } else {
+ TCGv_i32 res = tcg_temp_new_i32();
+ TCGv_i64 res64 = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_mul_i32(res, m1, m2);
+ tcg_gen_ext_i32_i64(res64, res);
+ tcg_gen_concat_i32_i64(tmp,
+ cpu_SR[ACCLO], cpu_SR[ACCHI]);
+ if (op == MAC16_MULA) {
+ tcg_gen_add_i64(tmp, tmp, res64);
+ } else {
+ tcg_gen_sub_i64(tmp, tmp, res64);
+ }
+ tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
+ tcg_gen_shri_i64(tmp, tmp, 32);
+ tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
+ tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
+
+ tcg_temp_free(res);
+ tcg_temp_free_i64(res64);
+ tcg_temp_free_i64(tmp);
+ }
+ tcg_temp_free(m1);
+ tcg_temp_free(m2);
+ }
+ if (ld_offset) {
+ tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
+ tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
+ }
+ tcg_temp_free(vaddr);
+ tcg_temp_free(mem32);
+ }
+ }
break;
case 5: /*CALLN*/
--
1.7.6.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Qemu-devel] [PATCH 2/2] target-xtensa: add MAC16 unit tests
2011-10-10 2:25 [Qemu-devel] [PATCH 0/2] target-xtensa: implement MAC16 option and unit tests for it Max Filippov
2011-10-10 2:25 ` [Qemu-devel] [PATCH 1/2] target-xtensa: implement MAC16 option Max Filippov
@ 2011-10-10 2:25 ` Max Filippov
2011-10-15 21:36 ` [Qemu-devel] [PATCH 0/2] target-xtensa: implement MAC16 option and unit tests for it Blue Swirl
2 siblings, 0 replies; 4+ messages in thread
From: Max Filippov @ 2011-10-10 2:25 UTC (permalink / raw)
To: qemu-devel; +Cc: jcmvbkbc
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/xtensa/Makefile | 1 +
tests/xtensa/test_mac16.S | 243 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 244 insertions(+), 0 deletions(-)
create mode 100644 tests/xtensa/test_mac16.S
diff --git a/tests/xtensa/Makefile b/tests/xtensa/Makefile
index 70bd097..15d39da 100644
--- a/tests/xtensa/Makefile
+++ b/tests/xtensa/Makefile
@@ -28,6 +28,7 @@ TESTCASES += test_clamps.tst
TESTCASES += test_fail.tst
TESTCASES += test_interrupt.tst
TESTCASES += test_loop.tst
+TESTCASES += test_mac16.tst
TESTCASES += test_max.tst
TESTCASES += test_min.tst
TESTCASES += test_mmu.tst
diff --git a/tests/xtensa/test_mac16.S b/tests/xtensa/test_mac16.S
new file mode 100644
index 0000000..5ddd160
--- /dev/null
+++ b/tests/xtensa/test_mac16.S
@@ -0,0 +1,243 @@
+.include "macros.inc"
+
+test_suite mac16
+
+#define ext16(v) (((v) & 0xffff) | (((v) & 0x8000) * 0x1ffffffe))
+#define mul16(a, b) ((ext16(a) * ext16(b)))
+
+.macro assert_acc_value v
+ rsr a4, ACCLO
+ movi a5, (\v) & 0xffffffff
+ assert eq, a4, a5
+ rsr a4, ACCHI
+ movi a5, (\v) >> 32
+ sext a5, a5, 7
+ assert eq, a4, a5
+.endm
+
+.macro init_reg sr, reg, val
+ .if (\sr)
+ movi a4, \val
+ wsr a4, \reg
+ .else
+ movi \reg, \val
+ .endif
+.endm
+
+.macro test_mulxx mulop, comb, s, t, a, b
+ init_reg \comb & 2, \s, \a
+ init_reg \comb & 1, \t, \b
+
+ \mulop\().ll \s, \t
+ assert_acc_value mul16(\a, \b)
+
+ \mulop\().lh \s, \t
+ assert_acc_value mul16(\a, (\b >> 16))
+
+ \mulop\().hl \s, \t
+ assert_acc_value mul16((\a >> 16), \b)
+
+ \mulop\().hh \s, \t
+ assert_acc_value mul16((\a >> 16), (\b >> 16))
+.endm
+
+test mul_aa
+ test_mulxx mul.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f
+test_end
+
+test mul_ad
+ test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f
+test_end
+
+test mul_da
+ test_mulxx mul.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f
+test_end
+
+test mul_dd
+ test_mulxx mul.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f
+test_end
+
+
+.macro init_acc iv
+ movi a4, (\iv) & 0xffffffff
+ wsr a4, ACCLO
+ movi a4, (\iv) >> 32
+ wsr a4, ACCHI
+.endm
+
+.macro test_mulxxx mulop, comb, s, t, a, b, iv, op
+ init_reg \comb & 2, \s, \a
+ init_reg \comb & 1, \t, \b
+
+ init_acc \iv
+ \mulop\().ll \s, \t
+ assert_acc_value (\iv \op mul16(\a, \b))
+
+ init_acc \iv
+ \mulop\().lh \s, \t
+ assert_acc_value (\iv \op mul16(\a, (\b >> 16)))
+
+ init_acc \iv
+ \mulop\().hl \s, \t
+ assert_acc_value (\iv \op mul16((\a >> 16), \b))
+
+ init_acc \iv
+ \mulop\().hh \s, \t
+ assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16)))
+.endm
+
+
+test mula_aa
+ test_mulxxx mula.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, +
+test_end
+
+test mula_ad
+ test_mulxxx mula.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, +
+test_end
+
+test mula_da
+ test_mulxxx mula.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+test_end
+
+test mula_dd
+ test_mulxxx mula.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+test_end
+
+
+test muls_aa
+ test_mulxxx muls.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, -
+test_end
+
+test muls_ad
+ test_mulxxx muls.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, -
+test_end
+
+test muls_da
+ test_mulxxx muls.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, -
+test_end
+
+test muls_dd
+ test_mulxxx muls.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, -
+test_end
+
+test ldinc
+ movi a2, 1f - 4
+ ldinc m0, a2
+ movi a3, 1f
+ assert eq, a2, a3
+ rsr a3, m0
+ movi a4, 0x55aa137f
+ assert eq, a3, a4
+ ldinc m1, a2
+ movi a3, 1f + 4
+ assert eq, a2, a3
+ rsr a3, m1
+ movi a4, 0x12345678
+ assert eq, a3, a4
+
+.data
+1: .word 0x55aa137f, 0x12345678, 0x137fa5a5
+.text
+test_end
+
+test lddec
+ movi a2, 1f
+ lddec m2, a2
+ movi a3, 1f - 4
+ assert eq, a2, a3
+ rsr a3, m2
+ movi a4, 0x12345678
+ assert eq, a3, a4
+ lddec m3, a2
+ movi a3, 1f - 8
+ assert eq, a2, a3
+ rsr a3, m3
+ movi a4, 0x55aa137f
+ assert eq, a3, a4
+.data
+ .word 0x55aa137f, 0x12345678
+1:
+.text
+test_end
+
+
+.macro test_mulxxx_ld mulop, ldop, comb, w, x, s, t, a, b, iv, op
+ init_reg \comb & 2, \s, \a
+ init_reg \comb & 1, \t, \b
+
+ init_acc \iv
+ \mulop\().ll.\ldop \w, \x, \s, \t
+ assert_acc_value (\iv \op mul16(\a, \b))
+
+ init_acc \iv
+ \mulop\().lh.\ldop \w, \x, \s, \t
+ assert_acc_value (\iv \op mul16(\a, (\b >> 16)))
+
+ init_acc \iv
+ \mulop\().hl.\ldop \w, \x, \s, \t
+ assert_acc_value (\iv \op mul16((\a >> 16), \b))
+
+ init_acc \iv
+ \mulop\().hh.\ldop \w, \x, \s, \t
+ assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16)))
+.endm
+
+test mula_da_ldinc
+ movi a2, 1f - 4
+ test_mulxxx_ld mula.da, ldinc, 2, m1, a2, m1, a3, \
+ 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+ movi a3, 1f + 12
+ assert eq, a2, a3
+ rsr a2, m1
+ movi a3, 0x12345678
+ assert eq, a2, a3
+.data
+1: .word 0xf7315a5a, 0xf7315a5a, 0xf7315a5a, 0x12345678
+.text
+test_end
+
+test mula_dd_ldinc
+ movi a2, 1f - 4
+ test_mulxxx_ld mula.dd, ldinc, 3, m2, a2, m1, m2, \
+ 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+ movi a3, 1f + 12
+ assert eq, a2, a3
+ rsr a2, m2
+ movi a3, 0x12345678
+ assert eq, a2, a3
+.data
+1: .word 0xa5a5137f, 0xa5a5137f, 0xa5a5137f, 0x12345678
+.text
+test_end
+
+test mula_da_lddec
+ movi a2, 1f
+ test_mulxxx_ld mula.da, lddec, 2, m1, a2, m1, a3, \
+ 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+ movi a3, 1f - 16
+ assert eq, a2, a3
+ rsr a2, m1
+ movi a3, 0x12345678
+ assert eq, a2, a3
+.data
+ .word 0x12345678, 0xf7315a5a, 0xf7315a5a, 0xf7315a5a
+1:
+.text
+test_end
+
+test mula_dd_lddec
+ movi a2, 1f
+ test_mulxxx_ld mula.dd, lddec, 3, m2, a2, m1, m2, \
+ 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, +
+ movi a3, 1f - 16
+ assert eq, a2, a3
+ rsr a2, m2
+ movi a3, 0x12345678
+ assert eq, a2, a3
+.data
+ .word 0x12345678, 0xa5a5137f, 0xa5a5137f, 0xa5a5137f
+1:
+.text
+test_end
+
+test_suite_end
--
1.7.6.4
^ permalink raw reply related [flat|nested] 4+ messages in thread