From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lei Wen Date: Mon, 31 Oct 2011 08:05:45 -0700 Subject: [U-Boot] [PATCH 1/2] pantheon: define CONFIG_SYS_CACHELINE_SIZE In-Reply-To: <1320073546-7277-1-git-send-email-leiwen@marvell.com> References: <1320073546-7277-1-git-send-email-leiwen@marvell.com> Message-ID: <1320073546-7277-2-git-send-email-leiwen@marvell.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de By default, on Pantheon SoC DCache Lnd ICache line lengths are 32 bytes long Signed-off-by: Lei Wen --- arch/arm/include/asm/arch-pantheon/config.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index d10583d..e4fce7d 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -28,6 +28,8 @@ #include #define CONFIG_ARM926EJS 1 /* Basic Architecture */ +/* default Dcache Line length for pantheon */ +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -- 1.7.0.4