From: Lei Wen <leiwen@marvell.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] armada100: define CONFIG_SYS_CACHELINE_SIZE
Date: Mon, 31 Oct 2011 08:05:46 -0700 [thread overview]
Message-ID: <1320073546-7277-3-git-send-email-leiwen@marvell.com> (raw)
In-Reply-To: <1320073546-7277-1-git-send-email-leiwen@marvell.com>
By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long
Signed-off-by: Lei Wen <leiwen@marvell.com>
---
arch/arm/include/asm/arch-armada100/config.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index d2094e5..637f313 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -33,6 +33,8 @@
#include <asm/arch/armada100.h>
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
--
1.7.0.4
next prev parent reply other threads:[~2011-10-31 15:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-31 15:05 [U-Boot] [PATCH 0/2] fix build error for pantheon and armada100 Lei Wen
2011-10-31 15:05 ` [U-Boot] [PATCH 1/2] pantheon: define CONFIG_SYS_CACHELINE_SIZE Lei Wen
2011-11-01 7:18 ` Prafulla Wadaskar
2011-10-31 15:05 ` Lei Wen [this message]
2011-11-01 7:18 ` [U-Boot] [PATCH 2/2] armada100: " Prafulla Wadaskar
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