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From: "Eric Bénard" <eric@eukrea.com>
To: barebox@lists.infradead.org
Subject: [PATCH 5/6] CPUIMX51: configure SD1 iomux when ESDHC is enabled
Date: Mon, 12 Dec 2011 22:19:38 +0100	[thread overview]
Message-ID: <1323724779-370-5-git-send-email-eric@eukrea.com> (raw)
In-Reply-To: <1323724779-370-1-git-send-email-eric@eukrea.com>

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index a128d50..a2db6d9 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -88,6 +88,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
 	MX51_PAD_NANDF_CS1__NANDF_CS1,
 	/* LCD BL */
 	MX51_PAD_DI1_D1_CS__GPIO3_4,
+#ifdef CONFIG_MCI_IMX_ESDHC
+	/* SD 1 */
+	MX51_PAD_SD1_CMD__SD1_CMD,
+	MX51_PAD_SD1_CLK__SD1_CLK,
+	MX51_PAD_SD1_DATA0__SD1_DATA0,
+	MX51_PAD_SD1_DATA1__SD1_DATA1,
+	MX51_PAD_SD1_DATA2__SD1_DATA2,
+	MX51_PAD_SD1_DATA3__SD1_DATA3,
+#endif
 };
 
 #define GPIO_LAN8700_RESET	(1 * 32 + 31)
-- 
1.7.6.4


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  parent reply	other threads:[~2011-12-12 21:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-12-12 21:19 [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Eric Bénard
2011-12-12 21:19 ` [PATCH 2/6] CPUIMX35: enable the watchdog clock asap Eric Bénard
2011-12-12 21:19 ` [PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache Eric Bénard
2011-12-13  9:42   ` Sascha Hauer
2011-12-12 21:19 ` [PATCH 4/6] CPUIMX51: fix environement Eric Bénard
2011-12-12 21:19 ` Eric Bénard [this message]
2011-12-12 21:19 ` [PATCH 6/6] CPUIMX51: update defconfig Eric Bénard
2011-12-13  9:44 ` [PATCH 1/6] i.MX25: fix LD16 & LD17 iomux Sascha Hauer

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