From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dario Faggioli Subject: [PATCH 2 of 2] Move IOMMU faults handling into softirq for AMD-Vi. Date: Mon, 19 Dec 2011 19:53:32 +0100 Message-ID: <1324320812.2599.34.camel@Solace> References: <1324319661.2599.28.camel@Solace> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============4826422079005817844==" Return-path: In-Reply-To: <1324319661.2599.28.camel@Solace> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com Cc: Wei Wang2 , Tim Deegan , "allen.m.kay@intel.com" , Jan Beulich List-Id: xen-devel@lists.xenproject.org --===============4826422079005817844== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-8wzlB1E7qvtUZsb481cE" --=-8wzlB1E7qvtUZsb481cE Content-Type: multipart/mixed; boundary="=-qLgAQfWdlgT4mNDc0MAK" --=-qLgAQfWdlgT4mNDc0MAK Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Dealing with interrupts from AMD-Vi IOMMU is deferred to a softirq-tasklet, raised by the actual IRQ handler. To avoid more interrupts being generated (because of further faults), they must be masked in the IOMMU within the low level IRQ handler and enabled back in the tasklet body. Notice that this may cause the log to overflow, but none of the existing entry will be overwritten. Signed-off-by: Dario Faggioli diff -r 12cc8fc9a908 xen/drivers/passthrough/amd/iommu_init.c --- a/xen/drivers/passthrough/amd/iommu_init.c Mon Dec 19 16:46:14 2011 +00= 00 +++ b/xen/drivers/passthrough/amd/iommu_init.c Mon Dec 19 16:46:39 2011 +00= 00 @@ -32,6 +32,8 @@ =20 static int __initdata nr_amd_iommus; =20 +static struct tasklet amd_iommu_fault_tasklet; + unsigned short ivrs_bdf_entries; static struct radix_tree_root ivrs_maps; struct list_head amd_iommu_head; @@ -522,12 +524,10 @@ static void parse_event_log_entry(struct } } =20 -static void amd_iommu_page_fault(int irq, void *dev_id, - struct cpu_user_regs *regs) +static void __do_amd_iommu_page_fault(struct amd_iommu *iommu) { u32 entry; unsigned long flags; - struct amd_iommu *iommu =3D dev_id; =20 spin_lock_irqsave(&iommu->lock, flags); amd_iommu_read_event_log(iommu); @@ -546,6 +546,43 @@ static void amd_iommu_page_fault(int irq spin_unlock_irqrestore(&iommu->lock, flags); } =20 +static void do_amd_iommu_page_fault(unsigned long data) +{ + struct amd_iommu *iommu; + + if ( list_empty(&amd_iommu_head) ) + { + AMD_IOMMU_DEBUG("no device found, something must be very wrong!\n")= ; + return; + } + + /* No matter from whom the interrupt came from, check all the + * IOMMUs present in the system. This allows for having just one + * tasklet (instead of one per each IOMMU) and should be more than + * fine, considering how rare the event of a fault should be. */ +for_each_amd_iommu ( iommu ) + __do_amd_iommu_page_fault(iommu); +} + +static void amd_iommu_page_fault(int irq, void *dev_id, + struct cpu_user_regs *regs) +{ + u32 entry; + unsigned long flags; + struct amd_iommu *iommu =3D dev_id; + + /* silence interrupts. The tasklet will enable them back */ + spin_lock_irqsave(&iommu->lock, flags); + entry =3D readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET); + iommu_clear_bit(&entry, IOMMU_STATUS_EVENT_LOG_INT_SHIFT); + writel(entry, iommu->mmio_base+IOMMU_STATUS_MMIO_OFFSET); + spin_unlock_irqrestore(&iommu->lock, flags); + + /* Flag the tasklet as runnable so that it can execute, clear + * the log and re-enable interrupts. */ + tasklet_schedule(&amd_iommu_fault_tasklet); +} + static int __init set_iommu_interrupt_handler(struct amd_iommu *iommu) { int irq, ret; @@ -884,6 +921,8 @@ int __init amd_iommu_init(void) if ( amd_iommu_init_one(iommu) !=3D 0 ) goto error_out; =20 + softirq_tasklet_init(&amd_iommu_fault_tasklet, do_amd_iommu_page_fault= , 0); + return 0; =20 error_out: --=20 <> (Raistlin Majere) ------------------------------------------------------------------- Dario Faggioli, http://retis.sssup.it/people/faggioli Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK) PhD Candidate, ReTiS Lab, Scuola Superiore Sant'Anna, Pisa (Italy) --=-qLgAQfWdlgT4mNDc0MAK Content-Disposition: attachment; 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