From: "Rémi Denis-Courmont" <remi@remlab.net>
To: Conor Dooley <conor@kernel.org>, Guo Ren <guoren@kernel.org>,
linux-riscv@lists.infradead.org
Cc: palmer@dabbelt.com, heiko@sntech.de, charlie@rivosinc.com,
Palmer Dabbelt <palmer@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org,
Jisheng Zhang <jszhang@kernel.org>
Subject: Re: [PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs
Date: Thu, 13 Jul 2023 21:50:08 +0300 [thread overview]
Message-ID: <13302652.uLZWGnKmhe@basile.remlab.net> (raw)
In-Reply-To: <1855588.tdWV9SEqCh@basile.remlab.net>
Le torstaina 13. heinäkuuta 2023, 21.47.29 EEST Rémi Denis-Courmont a écrit :
> __asm__ (
> "vsetvli zero, zero, e8, m1, ta, ma\n"
> "csrr %1, vtype\n" : "=r" (vtype) : "r" (0xC0));
The input operand is obviously bogus left-over, sorry.
--
Rémi Denis-Courmont
http://www.remlab.net/
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next prev parent reply other threads:[~2023-07-13 18:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 17:48 [PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs Conor Dooley
2023-07-13 16:36 ` Jisheng Zhang
2023-07-13 16:56 ` Palmer Dabbelt
2023-07-13 17:04 ` Conor Dooley
2023-07-13 17:12 ` Jisheng Zhang
2023-07-13 17:36 ` Conor Dooley
2023-07-13 18:20 ` Conor Dooley
2023-07-13 17:33 ` Guo Ren
2023-07-13 17:43 ` Palmer Dabbelt
2023-07-14 6:07 ` Guo Ren
2023-07-13 17:45 ` Conor Dooley
2023-07-14 6:14 ` Guo Ren
2023-07-14 11:10 ` Conor Dooley
2023-07-14 18:45 ` Conor Dooley
2023-07-15 6:11 ` Guo Ren
2023-07-15 6:07 ` Guo Ren
2023-07-13 18:47 ` Rémi Denis-Courmont
2023-07-13 18:50 ` Rémi Denis-Courmont [this message]
2023-07-14 19:21 ` Conor Dooley
2023-07-15 6:12 ` Guo Ren
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