From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH 1/7] drm/i915: implement ColorBlt w/a
Date: Sat, 31 Mar 2012 11:54:01 +0100
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On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> According to an internal workaround master list, we need to set bit 5
> of register 9400 to avoid issues with color blits.

This sounds like it could be the root cause behind the FBC + BLT hangs.
But not the XY_COPY hangs.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre