From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] drm/i915: l3 parity sysfs interface Date: Sat, 14 Apr 2012 00:24:03 +0100 Message-ID: <1334359471_417726@CP5-2952> References: <1334358314-9743-1-git-send-email-ben@bwidawsk.net> <1334358314-9743-3-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 98EAF9E740 for ; Fri, 13 Apr 2012 16:24:36 -0700 (PDT) In-Reply-To: <1334358314-9743-3-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Fri, 13 Apr 2012 16:05:14 -0700, Ben Widawsky wrote: > Dumb binary interfaces which allow root-only updates of our cache > remapping registers. See intel-gpu-tools for how this can/should be > used. Initial comments: don't bother posting a read just before a read, and do return errors from the sysfs read/write functions (the return value is signed for that purpose). A lesser issue is that if you are worried about necessity of posting-reads, you should also worry about the effect of the weak ordering of writes. -Chris -- Chris Wilson, Intel Open Source Technology Centre