From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] drm/i915: Enable the PCH PLL for all generations after link training Date: Mon, 14 May 2012 16:23:05 +0100 Message-ID: <1337008989_24144@CP5-2952> References: <1336899249-2612-1-git-send-email-chris@chris-wilson.co.uk> <1336899249-2612-2-git-send-email-chris@chris-wilson.co.uk> <20120514081213.76b208cb@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id B3EE89E7A8 for ; Mon, 14 May 2012 08:23:12 -0700 (PDT) In-Reply-To: <20120514081213.76b208cb@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 14 May 2012 08:12:13 -0700, Jesse Barnes wrote: > Thanks Chris. Only thing I'm not sure about is the LPT bit; does this > function do what we want there? The other patch transforms intel_pch_enable_pll (hmm, that's actually a better name ;-) into a no-op if the crtc does not require a pll. Which I think is the easier way of tracking PLLs - allocate on up front if the chipset/output requires a PLL and then we do no need any more checks other than has-pll? in the main body of the code. -Chris -- Chris Wilson, Intel Open Source Technology Centre