Re: [PATCH 07/11] drm/i915: disable DIP while changing the port

[Chris Wilson <chris@chris-wilson.co.uk>]

On Thu, 24 May 2012 17:49:49 -0300, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> The register specification says we need to do this.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c |   30 +++++++++++++++++++++++-------
>  1 file changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index ce68ec0..5bcd609 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -309,6 +309,7 @@ void g4x_set_infoframes(struct drm_encoder *encoder,
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	u32 reg = VIDEO_DIP_CTL;
>  	u32 val = I915_READ(reg);
> +	u32 port;
>  
>  	if (!intel_hdmi->has_hdmi_sink) {
>  		/* If the registers were not initialized yet, they might be
> @@ -329,18 +330,25 @@ void g4x_set_infoframes(struct drm_encoder *encoder,
>  		return;
>  	}
>  
> -	val &= ~VIDEO_DIP_PORT_MASK;
>  	switch (intel_hdmi->sdvox_reg) {
>  	case SDVOB:
> -		val |= VIDEO_DIP_PORT_B;
> +		port = VIDEO_DIP_PORT_B;
>  		break;
>  	case SDVOC:
> -		val |= VIDEO_DIP_PORT_C;
> +		port = VIDEO_DIP_PORT_C;
>  		break;
>  	default:
>  		return;
>  	}
>  
> +	if (port != (val & VIDEO_DIP_PORT_MASK)) {
> +		val &= ~VIDEO_DIP_ENABLE;
> +		val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
> +		I915_WRITE(reg, val);

When does this write latch? (i.e. do we need to wait upon any event or
timeout?) At the very least you probably want to flush the write (with a
 POSTING_READ) before continuing.

> +		val &= ~VIDEO_DIP_PORT_MASK;
> +		val |= port;
> +	}
> +
>  	val |= VIDEO_DIP_ENABLE;
>  	val &= ~VIDEO_DIP_ENABLE_VENDOR;
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre