From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 07/14] drm/i915: disable DIP while changing the port Date: Mon, 28 May 2012 16:42:54 -0300 Message-ID: <1338234182-5021-8-git-send-email-przanoni@gmail.com> References: <1338234182-5021-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-vb0-f49.google.com (mail-vb0-f49.google.com [209.85.212.49]) by gabe.freedesktop.org (Postfix) with ESMTP id F32799ED9F for ; Mon, 28 May 2012 12:43:26 -0700 (PDT) Received: by mail-vb0-f49.google.com with SMTP id fo1so2456625vbb.36 for ; Mon, 28 May 2012 12:43:26 -0700 (PDT) In-Reply-To: <1338234182-5021-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni The register specification says we need to do this. V2: Only write the register if the port is enabled. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_hdmi.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 620b0db..c858da9 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -317,6 +317,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 reg = VIDEO_DIP_CTL; u32 val = I915_READ(reg); + u32 port; /* If the registers were not initialized yet, they might be zeroes, * which means we're selecting the AVI DIP and we're setting its @@ -337,18 +338,26 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, return; } - val &= ~VIDEO_DIP_PORT_MASK; switch (intel_hdmi->sdvox_reg) { case SDVOB: - val |= VIDEO_DIP_PORT_B; + port = VIDEO_DIP_PORT_B; break; case SDVOC: - val |= VIDEO_DIP_PORT_C; + port = VIDEO_DIP_PORT_C; break; default: return; } + if (port != (val & VIDEO_DIP_PORT_MASK)) { + if (val & VIDEO_DIP_ENABLE) { + val &= ~VIDEO_DIP_ENABLE; + I915_WRITE(reg, val); + } + val &= ~VIDEO_DIP_PORT_MASK; + val |= port; + } + val |= VIDEO_DIP_ENABLE; val &= ~VIDEO_DIP_ENABLE_VENDOR; @@ -366,6 +375,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); + u32 port; /* See the big comment in g4x_set_infoframes() */ val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; @@ -378,21 +388,29 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, return; } - val &= ~VIDEO_DIP_PORT_MASK; switch (intel_hdmi->sdvox_reg) { case HDMIB: - val |= VIDEO_DIP_PORT_B; + port = VIDEO_DIP_PORT_B; break; case HDMIC: - val |= VIDEO_DIP_PORT_C; + port = VIDEO_DIP_PORT_C; break; case HDMID: - val |= VIDEO_DIP_PORT_D; + port = VIDEO_DIP_PORT_D; break; default: return; } + if (port != (val & VIDEO_DIP_PORT_MASK)) { + if (val & VIDEO_DIP_ENABLE) { + val &= ~VIDEO_DIP_ENABLE; + I915_WRITE(reg, val); + } + val &= ~VIDEO_DIP_PORT_MASK; + val |= port; + } + val |= VIDEO_DIP_ENABLE; val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); -- 1.7.10