[Qemu-devel] [PATCH v5 04/16] target-or32: Add interrupt support

[Jia Liu <proljc@gmail.com>]

Add OpenRISC interrupt support.

Signed-off-by: Jia Liu <proljc@gmail.com>
---
 cpu-exec.c                      |   17 +++++++++++++
 target-openrisc/Makefile.objs   |    2 +-
 target-openrisc/cpu.h           |    9 ++++++-
 target-openrisc/helper.h        |   25 +++++++++++++++++++
 target-openrisc/intrpt.c        |   44 +++++++++++++++++++++++++++++++++
 target-openrisc/intrpt_helper.c |   52 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 147 insertions(+), 2 deletions(-)
 create mode 100644 target-openrisc/helper.h
 create mode 100644 target-openrisc/intrpt_helper.c

diff --git a/cpu-exec.c b/cpu-exec.c
index 7d0d87b..1d2fe6b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -378,6 +378,23 @@ int cpu_exec(CPUArchState *env)
                         do_interrupt(env);
                         next_tb = 0;
                     }
+#elif defined(TARGET_OPENRISC)
+                    {
+                        int idx = -1;
+                        if ((interrupt_request & CPU_INTERRUPT_HARD)
+                            && (env->sr & SR_IEE)) {
+                            idx = EXCP_INT;
+                        }
+                        if ((interrupt_request & CPU_INTERRUPT_TIMER)
+                            && (env->sr & SR_TEE)) {
+                            idx = EXCP_TICK;
+                        }
+                        if (idx >= 0) {
+                            env->exception_index = idx;
+                            do_interrupt(env);
+                            next_tb = 0;
+                        }
+                    }
 #elif defined(TARGET_SPARC)
                     if (interrupt_request & CPU_INTERRUPT_HARD) {
                         if (cpu_interrupts_enabled(env) &&
diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs
index 21b76b2..65f9391 100644
--- a/target-openrisc/Makefile.objs
+++ b/target-openrisc/Makefile.objs
@@ -1,3 +1,3 @@
 obj-$(CONFIG_SOFTMMU) += machine.o
 obj-y += cpu.o intrpt.o mmu.o translate.o
-obj-y += mmu_helper.o
+obj-y += intrpt_helper.o mmu_helper.o
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 4143dca..337ec1b 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -62,6 +62,10 @@ enum {
 /* Internel flags, delay slot flag */
 #define D_FLAG    1
 
+/* Interrupt */
+#define NR_IRQS  32
+#define PIC_MASK 0xFFFFFFFF
+
 /* Verison Register */
 #define SPR_VR       0xFFFF003F
 
@@ -300,6 +304,7 @@ struct CPUOpenRISCState {
     uint32_t picsr;         /* Interrupt contrl register*/
 #endif
     uint32_t feature;       /* CPU Capabilities */
+    void *irq[32];          /* Interrupt irq input */
 };
 
 #define TYPE_OPENRISC_CPU "or32-cpu"
@@ -411,9 +416,11 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env)
     return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 }
 
+#define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
 static inline bool cpu_has_work(CPUOpenRISCState *env)
 {
-    return true;
+    return env->interrupt_request & (CPU_INTERRUPT_HARD |
+                                     CPU_INTERRUPT_TIMER);
 }
 
 #include "exec-all.h"
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
new file mode 100644
index 0000000..16d99b6
--- /dev/null
+++ b/target-openrisc/helper.h
@@ -0,0 +1,25 @@
+/*
+ *  OpenRISC helper defines
+ *
+ *  Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "def-helper.h"
+
+/* interrupt */
+DEF_HELPER_FLAGS_1(rfe, 0, void, env)
+
+#include "def-helper.h"
diff --git a/target-openrisc/intrpt.c b/target-openrisc/intrpt.c
index 72ee402..85f3d25 100644
--- a/target-openrisc/intrpt.c
+++ b/target-openrisc/intrpt.c
@@ -27,4 +27,48 @@
 
 void do_interrupt(CPUOpenRISCState *env)
 {
+#if !defined(CONFIG_USER_ONLY)
+    if (env->flags & D_FLAG) { /* Delay Slot insn */
+        env->flags &= ~D_FLAG;
+        env->sr |= SR_DSX;
+        if (env->exception_index == EXCP_TICK    ||
+            env->exception_index == EXCP_INT     ||
+            env->exception_index == EXCP_SYSCALL ||
+            env->exception_index == EXCP_FPE) {
+            env->epcr = env->jmp_pc;
+        } else {
+            env->epcr = env->pc - 4;
+        }
+    } else {
+        if (env->exception_index == EXCP_TICK    ||
+            env->exception_index == EXCP_INT     ||
+            env->exception_index == EXCP_SYSCALL ||
+            env->exception_index == EXCP_FPE) {
+            env->epcr = env->npc;
+        } else {
+            env->epcr = env->pc;
+        }
+    }
+
+    /* For machine-state changed between user-mode and supervisor mode,
+       we need flush TLB when we enter&exit EXCP.  */
+    tlb_flush(env, 1);
+
+    env->esr = env->sr;
+    env->sr &= ~SR_DME;
+    env->sr &= ~SR_IME;
+    env->sr |= SR_SM;
+    env->sr &= ~SR_IEE;
+    env->sr &= ~SR_TEE;
+    env->tlb->map_address_data = &get_phys_nommu;
+    env->tlb->map_address_code = &get_phys_nommu;
+
+    if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
+        env->pc = (env->exception_index << 8);
+    } else {
+        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+    }
+#endif
+
+    env->exception_index = -1;
 }
diff --git a/target-openrisc/intrpt_helper.c b/target-openrisc/intrpt_helper.c
new file mode 100644
index 0000000..0e4432e
--- /dev/null
+++ b/target-openrisc/intrpt_helper.c
@@ -0,0 +1,52 @@
+/*
+ *  OpenRISC interrupt helper routines
+ *
+ *  Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *                          Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+
+void HELPER(rfe)(CPUOpenRISCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+    int need_flush_tlb = (env->sr & (SR_SM | SR_IME | SR_DME)) ^
+                         (env->esr & (SR_SM | SR_IME | SR_DME));
+#endif
+    env->pc = env->epcr;
+    env->npc = env->epcr;
+    env->sr = env->esr;
+
+#if !defined(CONFIG_USER_ONLY)
+    if (env->sr & SR_DME) {
+        env->tlb->map_address_data = &get_phys_data;
+    } else {
+        env->tlb->map_address_data = &get_phys_nommu;
+    }
+
+    if (env->sr & SR_IME) {
+        env->tlb->map_address_code = &get_phys_code;
+    } else {
+        env->tlb->map_address_code = &get_phys_nommu;
+    }
+
+    if (need_flush_tlb) {
+        tlb_flush(env, 1);
+    }
+#endif
+    env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+}
-- 
1.7.9.5