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From: "Hervé Poussineau" <hpoussin@reactos.org>
To: qemu-devel@nongnu.org
Cc: "Blue Swirl" <blauwirbel@gmail.com>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Hervé Poussineau" <hpoussin@reactos.org>
Subject: [Qemu-devel] [PATCH 8/9] esp: use trace framework instead of stderr output
Date: Sun, 24 Jun 2012 19:15:41 +0200	[thread overview]
Message-ID: <1340558142-14532-9-git-send-email-hpoussin@reactos.org> (raw)
In-Reply-To: <1340558142-14532-1-git-send-email-hpoussin@reactos.org>


Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
 hw/esp.c     |   13 ++++++-------
 trace-events |    3 +++
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/esp.c b/hw/esp.c
index 796cdc1..ec40d93 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -26,6 +26,7 @@
 #include "scsi.h"
 #include "esp.h"
 #include "trace.h"
+#include "qemu-log.h"
 
 /*
  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
@@ -35,9 +36,6 @@
  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  */
 
-#define ESP_ERROR(fmt, ...)                                             \
-    do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
-
 #define ESP_REGS 16
 #define TI_BUFSZ 16
 
@@ -503,7 +501,8 @@ static uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
             s->ti_size--;
             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
                 /* Data out.  */
-                ESP_ERROR("PIO data read not implemented\n");
+                qemu_log_mask(LOG_UNIMP,
+                              "esp: PIO data read not implemented\n");
                 s->rregs[ESP_FIFO] = 0;
             } else {
                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
@@ -543,7 +542,7 @@ static void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
         if (s->do_cmd) {
             s->cmdbuf[s->cmdlen++] = val & 0xff;
         } else if (s->ti_size == TI_BUFSZ - 1) {
-            ESP_ERROR("fifo overrun\n");
+            trace_esp_error_fifo_overrun();
         } else {
             s->ti_size++;
             s->ti_buf[s->ti_wptr++] = val & 0xff;
@@ -631,7 +630,7 @@ static void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
             esp_raise_irq(s);
             break;
         default:
-            ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
+            trace_esp_error_unhandled_command(val);
             break;
         }
         break;
@@ -646,7 +645,7 @@ static void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
         s->rregs[saddr] = val;
         break;
     default:
-        ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
+        trace_esp_error_invalid_write(val, saddr);
         return;
     }
     s->wregs[saddr] = val;
diff --git a/trace-events b/trace-events
index 9b2e717..fa13aed 100644
--- a/trace-events
+++ b/trace-events
@@ -644,6 +644,9 @@ iscsi_aio_read16_cb(void *iscsi, int status, void *acb, int canceled) "iscsi %p
 iscsi_aio_readv(void *iscsi, int64_t sector_num, int nb_sectors, void *opaque, void *acb) "iscsi %p sector_num %"PRId64" nb_sectors %d opaque %p acb %p"
 
 # hw/esp.c
+esp_error_fifo_overrun(void) "FIFO overrun"
+esp_error_unhandled_command(uint32_t val) "unhandled command (%2.2x)"
+esp_error_invalid_write(uint32_t val, uint32_t addr) "invalid write of 0x%02x at [0x%x]"
 esp_raise_irq(void) "Raise IRQ"
 esp_lower_irq(void) "Lower IRQ"
 esp_dma_enable(void) "Raise enable"
-- 
1.7.10

  parent reply	other threads:[~2012-06-24 17:15 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-24 17:15 [Qemu-devel] [PATCH 0/7] esp: add AMD PCscsi emulation Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 1/9] esp: execute select commands immediately when it is a non-dma command Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 2/9] esp: delay Transfer Information command if dma is not enabled Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 3/9] esp: implement Disable selection command Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 4/9] esp: implement Reset ATN command Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 5/9] esp: support future change of chip_id Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 6/9] esp: use hba_private field instead of a complex cast Hervé Poussineau
2012-06-24 17:15 ` [Qemu-devel] [PATCH 7/9] esp: split esp code into generic chip emulation and sysbus layer Hervé Poussineau
2012-06-24 17:15 ` Hervé Poussineau [this message]
2012-06-24 19:38   ` [Qemu-devel] [PATCH 8/9] esp: use trace framework instead of stderr output Blue Swirl
2012-06-24 17:15 ` [Qemu-devel] [PATCH 9/9] esp: add AMD PCscsi emulation (PCI SCSI adapter) Hervé Poussineau

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