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From: Dave Airlie <airlied@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 1/3] drm: introduce pcie gen2 link speed check
Date: Tue, 26 Jun 2012 15:50:47 +0100	[thread overview]
Message-ID: <1340722249-27052-1-git-send-email-airlied@gmail.com> (raw)

From: Dave Airlie <airlied@redhat.com>

PCI express gen2.0 can support 5GT link speeds, this add code to
decide if this can be used for the device. We currently disable
it for via/serverengines root ports due to known issues.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_pci.c |   37 +++++++++++++++++++++++++++++++++++++
 include/drm/drmP.h        |    2 +-
 2 files changed, 38 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 13f3d93..e4918de 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -465,3 +465,40 @@ void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver)
 	DRM_INFO("Module unloaded\n");
 }
 EXPORT_SYMBOL(drm_pci_exit);
+
+int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev)
+{
+	struct pci_dev *root;
+	int pos;
+	u32 reg32;
+
+	if (!dev->pdev)
+		return -EINVAL;
+
+	if (!pci_is_pcie(dev->pdev))
+		return -EINVAL;
+
+	root = dev->pdev->bus->self;
+
+	pos = pci_pcie_cap(root);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_dword(root, pos + PCI_EXP_LNKCAP, &reg32);
+
+	reg32 &= PCI_EXP_LNKCAP_SLS;
+
+	/* we've been informed via and serverworks don't make the cut */
+	if (root->vendor == PCI_VENDOR_ID_VIA || root->vendor == PCI_VENDOR_ID_SERVERWORKS)
+		return -EINVAL;
+
+	DRM_INFO("probing gen 2 caps for device %x:%x = %x\n", root->vendor, root->device, reg32);
+	if (reg32 == 0x1)
+		return -EINVAL;
+
+	if (reg32 == 0x2)
+		return 0;
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(drm_pcie_is_5gt_link_speed_capable);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 31ad880..57d3e85 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1760,7 +1760,7 @@ extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
 extern int drm_get_pci_dev(struct pci_dev *pdev,
 			   const struct pci_device_id *ent,
 			   struct drm_driver *driver);
-
+extern int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev);
 
 /* platform section */
 extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
-- 
1.7.7.6

             reply	other threads:[~2012-06-26 14:55 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-26 14:50 Dave Airlie [this message]
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
2012-06-26 14:50 ` [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible Dave Airlie
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
2012-06-26 15:10   ` Dave Airlie
2012-06-26 15:33 ` Alex Deucher
2012-06-26 15:57   ` Dave Airlie

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