From: Dave Airlie <airlied@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible.
Date: Tue, 26 Jun 2012 15:50:49 +0100 [thread overview]
Message-ID: <1340722249-27052-3-git-send-email-airlied@gmail.com> (raw)
In-Reply-To: <1340722249-27052-1-git-send-email-airlied@gmail.com>
From: Dave Airlie <airlied@redhat.com>
This attempts to enable PCIE gen2 where possible, disabling
via radeon.pcie_gen2 in case of regression, so we can test it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/radeon/evergreen.c | 5 +++++
drivers/gpu/drm/radeon/r600.c | 5 +++++
drivers/gpu/drm/radeon/radeon_drv.c | 4 ++--
drivers/gpu/drm/radeon/rv770.c | 5 +++++
4 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f716e08..3a422a3 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3295,6 +3295,11 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev))
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 43d0c41..d7b62dc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3683,6 +3683,11 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
if (rdev->family <= CHIP_R600)
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
/* 55 nm r6xx asics */
if ((rdev->family == CHIP_RV670) ||
(rdev->family == CHIP_RV620) ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 2c4d53f..042fcff 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -133,7 +133,7 @@ int radeon_tv = 1;
int radeon_audio = 0;
int radeon_disp_priority = 0;
int radeon_hw_i2c = 0;
-int radeon_pcie_gen2 = 0;
+int radeon_pcie_gen2 = -1;
int radeon_msi = -1;
int radeon_lockup_timeout = 10000;
@@ -179,7 +179,7 @@ module_param_named(disp_priority, radeon_disp_priority, int, 0444);
MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
-MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)");
+MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b4f51c5..965745c 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1135,6 +1135,11 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev))
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
/* advertise upconfig capability */
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS;
--
1.7.7.6
next prev parent reply other threads:[~2012-06-26 14:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
2012-06-26 14:50 ` Dave Airlie [this message]
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
2012-06-26 15:10 ` Dave Airlie
2012-06-26 15:33 ` Alex Deucher
2012-06-26 15:57 ` Dave Airlie
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