* [PATCH 1/3] drm: introduce pcie gen2 link speed check
@ 2012-06-26 14:50 Dave Airlie
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Dave Airlie @ 2012-06-26 14:50 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
PCI express gen2.0 can support 5GT link speeds, this add code to
decide if this can be used for the device. We currently disable
it for via/serverengines root ports due to known issues.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/drm_pci.c | 37 +++++++++++++++++++++++++++++++++++++
include/drm/drmP.h | 2 +-
2 files changed, 38 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 13f3d93..e4918de 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -465,3 +465,40 @@ void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver)
DRM_INFO("Module unloaded\n");
}
EXPORT_SYMBOL(drm_pci_exit);
+
+int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev)
+{
+ struct pci_dev *root;
+ int pos;
+ u32 reg32;
+
+ if (!dev->pdev)
+ return -EINVAL;
+
+ if (!pci_is_pcie(dev->pdev))
+ return -EINVAL;
+
+ root = dev->pdev->bus->self;
+
+ pos = pci_pcie_cap(root);
+ if (!pos)
+ return -EINVAL;
+
+ pci_read_config_dword(root, pos + PCI_EXP_LNKCAP, ®32);
+
+ reg32 &= PCI_EXP_LNKCAP_SLS;
+
+ /* we've been informed via and serverworks don't make the cut */
+ if (root->vendor == PCI_VENDOR_ID_VIA || root->vendor == PCI_VENDOR_ID_SERVERWORKS)
+ return -EINVAL;
+
+ DRM_INFO("probing gen 2 caps for device %x:%x = %x\n", root->vendor, root->device, reg32);
+ if (reg32 == 0x1)
+ return -EINVAL;
+
+ if (reg32 == 0x2)
+ return 0;
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(drm_pcie_is_5gt_link_speed_capable);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 31ad880..57d3e85 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1760,7 +1760,7 @@ extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
extern int drm_get_pci_dev(struct pci_dev *pdev,
const struct pci_device_id *ent,
struct drm_driver *driver);
-
+extern int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev);
/* platform section */
extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
--
1.7.7.6
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/radeon: enable pcie gen2 on SI.
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
@ 2012-06-26 14:50 ` Dave Airlie
2012-06-26 14:50 ` [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible Dave Airlie
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Dave Airlie @ 2012-06-26 14:50 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
This patch assumes SI is the same as NI wrt gen2 enabling, and just
calls the evergreen code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/radeon/si.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 34603b3c8..406efa8 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -61,7 +61,7 @@ extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
-
+extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
/* get temperature in millidegrees */
int si_get_temp(struct radeon_device *rdev)
{
@@ -3650,6 +3650,8 @@ static int si_startup(struct radeon_device *rdev)
struct radeon_ring *ring;
int r;
+ evergreen_pcie_gen2_enable(rdev);
+
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
!rdev->rlc_fw || !rdev->mc_fw) {
r = si_init_microcode(rdev);
--
1.7.7.6
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible.
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
@ 2012-06-26 14:50 ` Dave Airlie
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
2012-06-26 15:33 ` Alex Deucher
3 siblings, 0 replies; 7+ messages in thread
From: Dave Airlie @ 2012-06-26 14:50 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
This attempts to enable PCIE gen2 where possible, disabling
via radeon.pcie_gen2 in case of regression, so we can test it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/radeon/evergreen.c | 5 +++++
drivers/gpu/drm/radeon/r600.c | 5 +++++
drivers/gpu/drm/radeon/radeon_drv.c | 4 ++--
drivers/gpu/drm/radeon/rv770.c | 5 +++++
4 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f716e08..3a422a3 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3295,6 +3295,11 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev))
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 43d0c41..d7b62dc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3683,6 +3683,11 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
if (rdev->family <= CHIP_R600)
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
/* 55 nm r6xx asics */
if ((rdev->family == CHIP_RV670) ||
(rdev->family == CHIP_RV620) ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 2c4d53f..042fcff 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -133,7 +133,7 @@ int radeon_tv = 1;
int radeon_audio = 0;
int radeon_disp_priority = 0;
int radeon_hw_i2c = 0;
-int radeon_pcie_gen2 = 0;
+int radeon_pcie_gen2 = -1;
int radeon_msi = -1;
int radeon_lockup_timeout = 10000;
@@ -179,7 +179,7 @@ module_param_named(disp_priority, radeon_disp_priority, int, 0444);
MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
-MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)");
+MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b4f51c5..965745c 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1135,6 +1135,11 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
if (ASIC_IS_X2(rdev))
return;
+ if (radeon_pcie_gen2 == -1 && drm_pcie_is_5gt_link_speed_capable(rdev->ddev) != 0)
+ return;
+
+ DRM_INFO("enabling PCIE gen 2 link speeds (disable with radeon.pcie_gen2=0\n");
+
/* advertise upconfig capability */
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS;
--
1.7.7.6
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm: introduce pcie gen2 link speed check
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
2012-06-26 14:50 ` [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible Dave Airlie
@ 2012-06-26 15:09 ` Adam Jackson
2012-06-26 15:10 ` Dave Airlie
2012-06-26 15:33 ` Alex Deucher
3 siblings, 1 reply; 7+ messages in thread
From: Adam Jackson @ 2012-06-26 15:09 UTC (permalink / raw)
To: Dave Airlie; +Cc: dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 579 bytes --]
On Tue, 2012-06-26 at 15:50 +0100, Dave Airlie wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> PCI express gen2.0 can support 5GT link speeds, this add code to
> decide if this can be used for the device. We currently disable
> it for via/serverengines root ports due to known issues.
^^^^^^^^^^^^^
Patch says ServerWorks. SE is Emulex, SW is Broadcom.
Seems a little like core PCIE functionality, but apparently we're the
first ones to want it so we can refactor later.
For the series:
Reviewed-by: Adam Jackson <ajax@redhat.com>
- ajax
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm: introduce pcie gen2 link speed check
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
@ 2012-06-26 15:10 ` Dave Airlie
0 siblings, 0 replies; 7+ messages in thread
From: Dave Airlie @ 2012-06-26 15:10 UTC (permalink / raw)
To: Adam Jackson; +Cc: dri-devel
On Tue, Jun 26, 2012 at 4:09 PM, Adam Jackson <ajax@redhat.com> wrote:
> On Tue, 2012-06-26 at 15:50 +0100, Dave Airlie wrote:
>> From: Dave Airlie <airlied@redhat.com>
>>
>> PCI express gen2.0 can support 5GT link speeds, this add code to
>> decide if this can be used for the device. We currently disable
>> it for via/serverengines root ports due to known issues.
> ^^^^^^^^^^^^^
>
> Patch says ServerWorks. SE is Emulex, SW is Broadcom.
Oops, good point, will fix commit message,
thanks,
Dave.
>
> Seems a little like core PCIE functionality, but apparently we're the
> first ones to want it so we can refactor later.
>
> For the series:
>
> Reviewed-by: Adam Jackson <ajax@redhat.com>
>
> - ajax
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm: introduce pcie gen2 link speed check
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
` (2 preceding siblings ...)
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
@ 2012-06-26 15:33 ` Alex Deucher
2012-06-26 15:57 ` Dave Airlie
3 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2012-06-26 15:33 UTC (permalink / raw)
To: Dave Airlie; +Cc: dri-devel
On Tue, Jun 26, 2012 at 10:50 AM, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> PCI express gen2.0 can support 5GT link speeds, this add code to
> decide if this can be used for the device. We currently disable
> it for via/serverengines root ports due to known issues.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
I need to double check that SI works the same as NI, but 1 and 3 are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/drm_pci.c | 37 +++++++++++++++++++++++++++++++++++++
> include/drm/drmP.h | 2 +-
> 2 files changed, 38 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
> index 13f3d93..e4918de 100644
> --- a/drivers/gpu/drm/drm_pci.c
> +++ b/drivers/gpu/drm/drm_pci.c
> @@ -465,3 +465,40 @@ void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver)
> DRM_INFO("Module unloaded\n");
> }
> EXPORT_SYMBOL(drm_pci_exit);
> +
> +int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev)
> +{
> + struct pci_dev *root;
> + int pos;
> + u32 reg32;
> +
> + if (!dev->pdev)
> + return -EINVAL;
> +
> + if (!pci_is_pcie(dev->pdev))
> + return -EINVAL;
> +
> + root = dev->pdev->bus->self;
> +
> + pos = pci_pcie_cap(root);
> + if (!pos)
> + return -EINVAL;
> +
> + pci_read_config_dword(root, pos + PCI_EXP_LNKCAP, ®32);
> +
> + reg32 &= PCI_EXP_LNKCAP_SLS;
> +
> + /* we've been informed via and serverworks don't make the cut */
> + if (root->vendor == PCI_VENDOR_ID_VIA || root->vendor == PCI_VENDOR_ID_SERVERWORKS)
> + return -EINVAL;
> +
> + DRM_INFO("probing gen 2 caps for device %x:%x = %x\n", root->vendor, root->device, reg32);
> + if (reg32 == 0x1)
> + return -EINVAL;
> +
> + if (reg32 == 0x2)
> + return 0;
> +
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL(drm_pcie_is_5gt_link_speed_capable);
> diff --git a/include/drm/drmP.h b/include/drm/drmP.h
> index 31ad880..57d3e85 100644
> --- a/include/drm/drmP.h
> +++ b/include/drm/drmP.h
> @@ -1760,7 +1760,7 @@ extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
> extern int drm_get_pci_dev(struct pci_dev *pdev,
> const struct pci_device_id *ent,
> struct drm_driver *driver);
> -
> +extern int drm_pcie_is_5gt_link_speed_capable(struct drm_device *dev);
>
> /* platform section */
> extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
> --
> 1.7.7.6
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm: introduce pcie gen2 link speed check
2012-06-26 15:33 ` Alex Deucher
@ 2012-06-26 15:57 ` Dave Airlie
0 siblings, 0 replies; 7+ messages in thread
From: Dave Airlie @ 2012-06-26 15:57 UTC (permalink / raw)
To: Alex Deucher; +Cc: dri-devel
On Tue, Jun 26, 2012 at 4:33 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> On Tue, Jun 26, 2012 at 10:50 AM, Dave Airlie <airlied@gmail.com> wrote:
>> From: Dave Airlie <airlied@redhat.com>
>>
>> PCI express gen2.0 can support 5GT link speeds, this add code to
>> decide if this can be used for the device. We currently disable
>> it for via/serverengines root ports due to known issues.
>>
>> Signed-off-by: Dave Airlie <airlied@redhat.com>
>
> I need to double check that SI works the same as NI, but 1 and 3 are:
>
Yeah after thinking about is SI might support 3.0 so it might be
different alright.
I also need to change the drm interface for 3.0.
Dave.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2012-06-26 15:57 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-06-26 14:50 [PATCH 1/3] drm: introduce pcie gen2 link speed check Dave Airlie
2012-06-26 14:50 ` [PATCH 2/3] drm/radeon: enable pcie gen2 on SI Dave Airlie
2012-06-26 14:50 ` [PATCH 3/3] drm/radeon: try to enable pcie gen2 where possible Dave Airlie
2012-06-26 15:09 ` [PATCH 1/3] drm: introduce pcie gen2 link speed check Adam Jackson
2012-06-26 15:10 ` Dave Airlie
2012-06-26 15:33 ` Alex Deucher
2012-06-26 15:57 ` Dave Airlie
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