All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andi Kleen <andi@firstfloor.org>
To: x86@kernel.org
Cc: a.p.zijlstra@chello.nl, linux-kernel@vger.kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3
Date: Mon,  2 Jul 2012 11:43:14 -0700	[thread overview]
Message-ID: <1341254598-1379-2-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1341254598-1379-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

Fork the IvyBridge support from the Sandy Bridge support to enable
some ivy specific features.

Very similar to Sandy Bridge, but:
- there is no PEBS problem.
- As Stephane pointed out .code=0xb1, .umask=0x01 is gone from the event list,
so don't do a generic backend stall event on IvyBridge.
- more changes in the next patch

v2: Remove stall event
v3: rebase to new code. completely separate switch case statement as shared
code was deemed obfuscated.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   23 ++++++++++++++++++++++-
 1 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index e23e71f..a741505 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1913,7 +1913,6 @@ __init int intel_pmu_init(void)
 	case 42: /* SandyBridge */
 	case 45: /* SandyBridge, "Romely-EP" */
 		x86_add_quirk(intel_sandybridge_quirk);
-	case 58: /* IvyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 
@@ -1937,6 +1936,28 @@ __init int intel_pmu_init(void)
 		pr_cont("SandyBridge events, ");
 		break;
 
+	case 58: /* IvyBridge */
+		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
+		       sizeof(hw_cache_event_ids));
+
+		intel_pmu_lbr_init_snb();
+
+		x86_pmu.event_constraints = intel_snb_event_constraints;
+		x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
+		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
+		x86_pmu.extra_regs = intel_snb_extra_regs;
+		/* all extra regs are per-cpu when HT is on */
+		x86_pmu.er_flags |= ERF_HAS_RSP_1;
+		x86_pmu.er_flags |= ERF_NO_HT_SHARING;
+
+		/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
+			X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+		/* no backend event */
+	      
+		pr_cont("IvyBridge events, ");
+		break;
+
 	default:
 		switch (x86_pmu.version) {
 		case 1:
-- 
1.7.7.6


  reply	other threads:[~2012-07-02 18:44 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-02 18:43 Updated and combined Sandy Bridge/Ivy Bridge perf patchkits Andi Kleen
2012-07-02 18:43 ` Andi Kleen [this message]
2012-07-02 19:26   ` [PATCH 1/5] perf, x86: Improve basic Ivy Bridge support v3 Peter Zijlstra
2012-07-02 19:58     ` Andi Kleen
2012-07-02 20:18       ` Peter Zijlstra
2012-07-02 18:43 ` [PATCH 2/5] perf, x86: Enable PDIR precise instruction profiling on IvyBridge Andi Kleen
2012-07-02 19:18   ` Peter Zijlstra
2012-07-02 19:57     ` Andi Kleen
2012-07-02 20:22       ` Peter Zijlstra
2012-07-02 21:00         ` Andi Kleen
2012-07-02 21:36           ` Peter Zijlstra
2012-07-02 21:57             ` Andi Kleen
2012-07-02 23:13               ` Stephane Eranian
2012-07-03  4:04                 ` Andi Kleen
2012-07-05 15:45                   ` Stephane Eranian
2012-07-05 17:26                     ` Andi Kleen
2012-07-06  1:04                       ` Stephane Eranian
2012-07-02 18:43 ` [PATCH 3/5] x86: Do microcode updates at CPU_STARTING, not CPU_ONLINE v2 Andi Kleen
2012-07-02 18:43 ` [PATCH 4/5] perf, x86: check ucode before disabling PEBS on SandyBridge v4 Andi Kleen
2012-07-02 18:43 ` [PATCH 5/5] perf, x86: Spell Romley correctly Andi Kleen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1341254598-1379-2-git-send-email-andi@firstfloor.org \
    --to=andi@firstfloor.org \
    --cc=a.p.zijlstra@chello.nl \
    --cc=ak@linux.intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.