From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+
Date: Thu, 05 Jul 2012 11:29:10 +0100 [thread overview]
Message-ID: <1341484214_176904@CP5-2952> (raw)
In-Reply-To: <1341483450-6385-2-git-send-email-daniel.vetter@ffwll.ch>
On Thu, 5 Jul 2012 12:17:30 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> The tileoffset register only supports a limited offset in x/y of 4096,
> so for giant screen configuration with a shared fb we wrap around.
>
> Fix this by computing a linear offset in tiles (pages) and only use
> the tileoffset register to offset within the tile.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Both Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
We could do with validating that the CRTC is within the fb->obj,
otherwise we run foul of hanging the hardware. (Since this is a
pre-existing condition it doesn't mar these patches.)
So the only question is whether we indicate to userspace that the kernel
is fixed? Or just kill the w/a in userspace and for reasons of sanity
strongly encourage everyone who hits this to upgrade? Since this is no
stable material, having keeping the w/a seems to make sense...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-07-05 10:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-05 10:17 [PATCH 1/2] drm/i915: introduce crtc->dspaddr_offset Daniel Vetter
2012-07-05 10:17 ` [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+ Daniel Vetter
2012-07-05 10:29 ` Chris Wilson [this message]
2012-07-05 11:38 ` Daniel Vetter
2012-07-05 10:37 ` Chris Wilson
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