From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Subject: [PATCH 2/2] radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG Date: Sun, 29 Jul 2012 16:02:02 +0200 Message-ID: <1343570522-4080-2-git-send-email-maraeo@gmail.com> References: <1343570522-4080-1-git-send-email-maraeo@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C1939E81F for ; Sun, 29 Jul 2012 07:02:14 -0700 (PDT) Received: by weyr3 with SMTP id r3so3432771wey.36 for ; Sun, 29 Jul 2012 07:02:14 -0700 (PDT) In-Reply-To: <1343570522-4080-1-git-send-email-maraeo@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth. --- radeon/radeon_surface.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 5800c33..fcfefdc 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -604,7 +604,10 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, } } - if (surf->flags & RADEON_SURF_SBUFFER) { + /* The depth and stencil buffers are in separate resources on evergreen. + * We allocate them in one buffer next to each other to simplify + * communication between the DDX and the Mesa driver. */ + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4; } @@ -752,14 +755,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - if (surf->flags & RADEON_SURF_SBUFFER) { - surf->flags |= RADEON_SURF_ZBUFFER; - } - if (surf->flags & RADEON_SURF_ZBUFFER) { + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { /* zbuffer only support 1D or 2D tiled surface */ switch (mode) { case RADEON_SURF_MODE_1D: @@ -828,11 +824,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - /* set some default value to avoid sanity check choking on them */ surf->tile_split = 1024; surf->bankw = 1; -- 1.7.9.5