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From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 3/8] drm/i915: correctly set the DDI_FUNC_CTL bpc field
Date: Wed,  8 Aug 2012 14:15:29 -0300	[thread overview]
Message-ID: <1344446134-3704-4-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1344446134-3704-1-git-send-email-przanoni@gmail.com>

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Correctly erase the values previously set and also check for 6pbc and
10bpc.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++++++------
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 896b279..f3fafb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4308,6 +4308,7 @@
 #define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
 #define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)
 #define  PIPE_DDI_MODE_SELECT_FDI		(4<<24)
+#define  PIPE_DDI_BPC_MASK			(7<<20)
 #define  PIPE_DDI_BPC_8					(0<<20)
 #define  PIPE_DDI_BPC_10				(1<<20)
 #define  PIPE_DDI_BPC_6					(2<<20)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1fbd67c..8b38359 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
 	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 	temp = I915_READ(DDI_FUNC_CTL(pipe));
 	temp &= ~PIPE_DDI_PORT_MASK;
-	temp &= ~PIPE_DDI_BPC_12;
+	temp &= ~PIPE_DDI_BPC_MASK;
 	temp &= ~PIPE_DDI_MODE_SELECT_MASK;
 	temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);
-	temp |= PIPE_DDI_SELECT_PORT(port) |
-			((intel_crtc->bpp > 24) ?
-				PIPE_DDI_BPC_12 :
-				PIPE_DDI_BPC_8) |
-			PIPE_DDI_FUNC_ENABLE;
+	temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);
+
+	switch (intel_crtc->bpp) {
+	case 18:
+		temp |= PIPE_DDI_BPC_6;
+		break;
+	case 24:
+		temp |= PIPE_DDI_BPC_8;
+		break;
+	case 30:
+		temp |= PIPE_DDI_BPC_10;
+		break;
+	case 36:
+		temp |= PIPE_DDI_BPC_12;
+		break;
+	default:
+		WARN(1, "%d bpp unsupported by pipe DDI function\n",
+		     intel_crtc->bpp);
+	}
 
 	if (intel_hdmi->has_hdmi_sink)
 		temp |= PIPE_DDI_MODE_SELECT_HDMI;
-- 
1.7.11.2

  parent reply	other threads:[~2012-08-08 17:16 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-08 17:15 [PATCH 0/8] Haswell HDMI fixes Paulo Zanoni
2012-08-08 17:15 ` [PATCH 1/8] drm/i915: fix pipe DDI mode select Paulo Zanoni
2012-08-08 17:15 ` [PATCH 2/8] drm/i915: set the DDI sync polarity bits Paulo Zanoni
2012-08-08 17:15 ` Paulo Zanoni [this message]
2012-08-09  9:55   ` [PATCH 3/8] drm/i915: correctly set the DDI_FUNC_CTL bpc field Jani Nikula
2012-08-09 16:40     ` Daniel Vetter
2012-08-09 16:46       ` Paulo Zanoni
2012-08-08 17:15 ` [PATCH 4/8] drm/i915: completely reset the value of DDI_FUNC_CTL Paulo Zanoni
2012-08-08 17:15 ` [PATCH 5/8] drm/i915: reindent Haswell register definitions Paulo Zanoni
2012-08-08 17:15 ` [PATCH 6/8] drm/i915: add parentheses around PIXCLK_GATE definitions Paulo Zanoni
2012-08-09 16:43   ` Daniel Vetter
2012-08-08 17:15 ` [PATCH 7/8] drm/i915: try harder to find WR PLL clock settings Paulo Zanoni
2012-08-09 10:56   ` Jani Nikula
2012-08-09 17:30     ` Paulo Zanoni
2012-08-09 17:38       ` Daniel Vetter
2012-08-08 17:15 ` [PATCH 8/8] drm/i915: try to use WR PLL 2 Paulo Zanoni
2012-08-09 11:32   ` Jani Nikula
2012-08-09 11:40 ` [PATCH 0/8] Haswell HDMI fixes Jani Nikula
2012-08-10 13:03 ` [PATCH] drm/i915: try harder to find WR PLL clock settings Paulo Zanoni
2012-08-10 13:18   ` Jani Nikula
2012-08-10 16:40     ` Daniel Vetter

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