[Qemu-devel] [PATCH v3 00/10] target-xtensa: implement FP coprocessor option

[Max Filippov <jcmvbkbc@gmail.com>]

This series implements floating point coprocessor and coprocessor context
options for xtensa and fixes a couple of bugs to make it work.

Changes v2->v3:
- add comment to the NO_SIGNALING_NANS definition
- reword explanation for UTRUNC.S

Changes v1->v2:
- add NO_SIGNALING_NANS and drop float32_maybe_silence_nan specialization
- fix fp registers access in gdbstub
- replace float32_mul/div in FP-to-integer convertors with float32_scalbn
- reimplement comparison with zero in FP-to-integer convertors

Max Filippov (10):
  softfloat: make float_muladd_negate_* flags independent
  softfloat: add NO_SIGNALING_NANS
  target-xtensa: handle boolean option in overlays
  target-xtensa: specialize softfloat NaN rules
  target-xtensa: add FP registers
  target-xtensa: implement LSCX and LSCI groups
  target-xtensa: implement FP0 arithmetic
  target-xtensa: implement FP0 conversions
  target-xtensa: implement FP1 group
  target-xtensa: implement coprocessor context option

 fpu/softfloat-specialize.h   |   72 +++++++++-
 fpu/softfloat.h              |    7 +-
 gdbstub.c                    |    8 +
 target-xtensa/cpu.h          |    8 +
 target-xtensa/helper.h       |   21 +++
 target-xtensa/op_helper.c    |  134 +++++++++++++++++
 target-xtensa/overlay_tool.h |    1 +
 target-xtensa/translate.c    |  338 ++++++++++++++++++++++++++++++++++++++++--
 8 files changed, 573 insertions(+), 16 deletions(-)

-- 
1.7.7.6