From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFOA4-0003a4-M0 for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFOA3-0004zT-Qo for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:16 -0400 Received: from mout.web.de ([212.227.17.11]:49775) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFOA3-0004zB-GB for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:15 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 22 Sep 2012 13:45:53 +0200 Message-Id: <1348314355-10992-1-git-send-email-andreas.faerber@web.de> In-Reply-To: <505C9E59.2040308@suse.de> References: <505C9E59.2040308@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [RFC v2 1/2] target-arm: Prepare support for Cortex-R4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: giancarlo.asnaghi@st.com, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Peter Maydell Glue "cortex-r4" to r1p4, the latest available TRM. Set MPU and Thumb division feature bit. Signed-off-by: Andreas Färber --- target-arm/cpu.c | 24 ++++++++++++++++++++++++ 1 Datei geändert, 24 Zeilen hinzugefügt(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index b00f5fa..6726498 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -382,6 +382,29 @@ static void cortex_m3_initfn(Object *obj) cpu->midr = 0x410fc231; } +static void cortex_r4_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); + set_feature(&cpu->env, ARM_FEATURE_MPU); + cpu->midr = 0x411FC144; /* r1p4 */ + cpu->id_pfr0 = 0x0131; + cpu->id_pfr1 = 0x001; + cpu->id_dfr0 = 0x010400; + cpu->id_afr0 = 0x0; + cpu->id_mmfr0 = 0x0210030; + cpu->id_mmfr1 = 0x00000000; + cpu->id_mmfr2 = 0x01200000; + cpu->id_mmfr3 = 0x0211; + cpu->id_isar0 = 0x1101111; + cpu->id_isar1 = 0x13112111; + cpu->id_isar2 = 0x21232131; + cpu->id_isar3 = 0x01112131; + cpu->id_isar4 = 0x0010142; + cpu->id_isar5 = 0x0; +} + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -737,6 +760,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm1176", .initfn = arm1176_initfn }, { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn }, + { .name = "cortex-r4", .initfn = cortex_r4_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, -- 1.7.10.4