All of lore.kernel.org
 help / color / mirror / Atom feed
From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 27/28] powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
Date: Tue, 23 Oct 2012 20:40:20 -0500	[thread overview]
Message-ID: <1351042820.7132.14@snotra> (raw)
In-Reply-To: <1349718271-26503-27-git-send-email-yorksun@freescale.com> (from yorksun@freescale.com on Mon Oct  8 12:44:30 2012)

On 10/08/2012 12:44:30 PM, York Sun wrote:
> Move spin table to cached memory to comply with ePAPR v1.1.
> Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
> 
> 'M' bit is set for DDR TLB to maintain cache coherence.
> 
> See details in doc/README.mpc85xx-spin-table.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
>  README                                    |    6 +
>  arch/powerpc/cpu/mpc85xx/fdt.c            |   13 ++-
>  arch/powerpc/cpu/mpc85xx/mp.c             |   61 +++++-----
>  arch/powerpc/cpu/mpc85xx/mp.h             |    5 +-
>  arch/powerpc/cpu/mpc85xx/release.S        |  179  
> +++++++++++++++++------------
>  arch/powerpc/cpu/mpc85xx/tlb.c            |    2 +-
>  arch/powerpc/include/asm/config_mpc85xx.h |    3 +
>  doc/README.mpc85xx-spin-table             |   26 +++++
>  8 files changed, 183 insertions(+), 112 deletions(-)
>  create mode 100644 doc/README.mpc85xx-spin-table

As we discussed internally, this patch needs to be RFC until changes go  
into Linux to be compatible with a cacheable spin table.

-Scott

  reply	other threads:[~2012-10-24  1:40 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-08 17:44 [U-Boot] [PATCH 01/28] driver/pci: Fix compiling error York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 02/28] powerpc/DPAA: " York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 03/28] powerpc/85xx: Add determining and report IFC frequency York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 04/28] powerpc/mpc85xx: Introduce new macros to add and delete TLB entries York Sun
2012-10-22  9:14   ` Andy Fleming
2012-10-22 16:16     ` York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 05/28] powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 06/28] powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 07/28] powerpc/mpc85xx: check number of cores York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 08/28] powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 09/28] powerpc/mpc85xx: expand SERDES reference clock select bit York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 10/28] powerpc/e6500: Move QCSP registers for QMan v3 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 11/28] powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 12/28] powerpc/corenet2: Add " York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 13/28] powerpc/corenet2: fix mismatch DDR sync bit from RCW York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 14/28] board/freescale/common: VSC3316/VSC3308 initialization code York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 15/28] powerpc/mpc85xx: Add T4 device definitions York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 16/28] powerpc/mpc85xx: Add T4240 SoC York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 17/28] powerpc/mpc85xx: Add B4860 and variant SoCs York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 18/28] fm/mEMAC: add mEMAC frame work York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 19/28] powerpc/mpc8xxx: Update DDR registers York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 20/28] powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 21/28] powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 22/28] powerpc/mpc85xx: software workaround for DDR erratum A-004468 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 23/28] powerpc/mpc85xx: Add workaround for DDR erratum A004934 York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 24/28] powerpc/mpc8xxx: Add auto select bank interleaving mode York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 25/28] powerpc/mpc8xxx: Fix DDR SPD failed message York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 26/28] powerpc/mpc85xx: Remove R6 from spin table York Sun
2012-10-08 17:44 ` [U-Boot] [PATCH 27/28] powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 York Sun
2012-10-24  1:40   ` Scott Wood [this message]
2012-10-08 17:44 ` [U-Boot] [PATCH 28/28] powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform York Sun

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1351042820.7132.14@snotra \
    --to=scottwood@freescale.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.