From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 09/10 v2] drm/i915: flush system agent TLBs on SNB Date: Fri, 26 Oct 2012 13:55:05 -0700 Message-ID: <1351284905-3644-1-git-send-email-ben@bwidawsk.net> References: <1350956055-3224-10-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id A2B54A0DC5 for ; Fri, 26 Oct 2012 13:55:11 -0700 (PDT) In-Reply-To: <1350956055-3224-10-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org This allows us to map the PTEs WC. I've not done thorough testing or performance measurements with this patch, but it should be decent. This is based on a patch from Jesse with the original commit message > I've only lightly tested this so far, but the corruption seems to be > gone if I write the GFX_FLSH_CNTL reg after binding an object. This > register should control the TLB for the system agent, which is what CPU > mapped objects will go through. It has been updated for the new AGP-less code by me, and included with it is feedback from the original patch. v2: Updated to reflect paranoia on pte updates/register posting reads. This entails doing the flush (with posting_read) after the pte readback Signed-off-by: Ben Widawsky Reviewed-by [v1]: Jesse Barnes --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +++++++++-- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f832ab0..47a408a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -402,6 +402,13 @@ out: * hardware should work, we must keep this posting read for paranoia. */ WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level)); + + /* This next bit makes the above posting read even more important. We + * want to flush the TLBs only after we're certain all the PTE updates + * have finished. + */ + I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); + POSTING_READ(GFX_FLSH_CNTL_GEN6); } void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, @@ -599,8 +606,8 @@ int i915_gem_gtt_init(struct drm_device *dev) if (ret) return ret; - dev_priv->mm.gtt->gtt = ioremap(gtt_bus_addr, - dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t)); + dev_priv->mm.gtt->gtt = ioremap_wc(gtt_bus_addr, + dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t)); /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */ DRM_DEBUG_DRIVER("GMADR size = %dM\n", dev_priv->mm.gtt->gtt_mappable_entries >> 8); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1d54328..e8c578f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -683,6 +683,8 @@ #define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ +#define GFX_FLSH_CNTL_GEN6 0x101008 +#define GFX_FLSH_CNTL_EN (1<<0) #define ECOSKPD 0x021d0 #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) -- 1.8.0