From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 02/10] drm/i915: fix FDI lane calculation Date: Tue, 20 Nov 2012 13:27:36 -0200 Message-ID: <1353425264-3728-3-git-send-email-przanoni@gmail.com> References: <1353425264-3728-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 73F4FE6325 for ; Tue, 20 Nov 2012 07:28:01 -0800 (PST) Received: by mail-gg0-f177.google.com with SMTP id y3so680521ggc.36 for ; Tue, 20 Nov 2012 07:28:01 -0800 (PST) In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni The previous code was making the bps value 5% higher than what the spec says, which was enough to make certain VGA modes require 3 lanes instead of 2, which breaks Haswell since it only has 2 FDI lanes. For previous gens this was not a problem, since requiring more lanes than the needed is ok, as long as you have all the lanes. Notice that this might improve the case where we use pipes B and C on Ivy Bridge since both pipes only have 4 lanes to share (see ironlake_check_fdi_lanes). We still need to code to refuse modes requiring more than 2 lanes on Haswell. Cc: Adam Jackson Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0102931..9940765 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5272,14 +5272,15 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, if (!lane) { /* - * Account for spread spectrum to avoid - * oversubscribing the link. Max center spread - * is 2.5%; use 5% for safety's sake. + * The spec says: + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) */ - u32 bps = target_clock * intel_crtc->bpp * 21 / 20; - lane = bps / (link_bw * 8) + 1; + u32 bps = target_clock * intel_crtc->bpp; + lane = DIV_ROUND_UP(bps, (link_bw * 8)); } + DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane, + pipe_name(intel_crtc->pipe)); intel_crtc->fdi_lanes = lane; if (pixel_multiplier > 1) -- 1.7.11.7