From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 3/3] drm/i915: fix FDI lane calculation Date: Thu, 29 Nov 2012 11:29:33 -0200 Message-ID: <1354195773-4022-3-git-send-email-przanoni@gmail.com> References: <1354195773-4022-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id CE3ACE65B6 for ; Thu, 29 Nov 2012 05:29:53 -0800 (PST) Received: by mail-gg0-f177.google.com with SMTP id y3so2575514ggc.36 for ; Thu, 29 Nov 2012 05:29:53 -0800 (PST) In-Reply-To: <1354195773-4022-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni The previous code was making the bps value 5% higher than what the spec says, which was enough to make certain VGA modes require 3 lanes instead of 2, which makes us reject these modes on Haswell since it only has 2 FDI lanes. For previous gens this was not much of a problem, since they had 4 lanes, and requiring more lanes than the needed is ok, as long as you have all the lanes. Notice that this might improve the case where we use pipes B and C on Ivy Bridge since both pipes only have 4 lanes to share (see ironlake_check_fdi_lanes). Cc: Adam Jackson Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) As it is, this one will make the list of supported modes on Haswell VGA bigger, so we could skip 3.8 and send this through 3.9, so we have plently of time to get confident this won't break older platforms. diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8d86a39..1825ae7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5231,12 +5231,10 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) { /* - * Account for spread spectrum to avoid - * oversubscribing the link. Max center spread - * is 2.5%; use 5% for safety's sake. + * The spec says: + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) */ - u32 bps = target_clock * bpp * 21 / 20; - return bps / (link_bw * 8) + 1; + return DIV_ROUND_UP(target_clock * bpp, link_bw * 8); } static void ironlake_set_m_n(struct drm_crtc *crtc, @@ -5296,6 +5294,8 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, lane = ironlake_get_lanes_required(target_clock, link_bw, intel_crtc->bpp); + DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane, + pipe_name(intel_crtc->pipe)); intel_crtc->fdi_lanes = lane; if (pixel_multiplier > 1) -- 1.7.11.7