From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TiDqT-0003QE-Js for qemu-devel@nongnu.org; Mon, 10 Dec 2012 19:37:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TiDqO-000112-7i for qemu-devel@nongnu.org; Mon, 10 Dec 2012 19:37:13 -0500 Date: Mon, 10 Dec 2012 18:36:55 -0600 From: Scott Wood In-Reply-To: <1354974282-1915-17-git-send-email-agraf@suse.de> (from agraf@suse.de on Sat Dec 8 07:44:39 2012) Message-ID: <1355186215.5334.21@snotra> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; delsp=Yes; format=Flowed Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/19] openpic: add Shared MSI support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "qemu-ppc@nongnu.org List" , qemu-devel qemu-devel On 12/08/2012 07:44:39 AM, Alexander Graf wrote: > The OpenPIC allows MSI access through shared MSI registers. Implement > them for the MPC8544 MPIC, so we can support MSIs. >=20 > Signed-off-by: Alexander Graf > --- > hw/openpic.c | 150 =20 > ++++++++++++++++++++++++++++++++++++++++++++++++++-------- > 1 files changed, 130 insertions(+), 20 deletions(-) >=20 > diff --git a/hw/openpic.c b/hw/openpic.c > index f2f152f..f71d668 100644 > --- a/hw/openpic.c > +++ b/hw/openpic.c > @@ -38,6 +38,7 @@ > #include "pci.h" > #include "openpic.h" > #include "sysbus.h" > +#include "msi.h" >=20 > //#define DEBUG_OPENPIC >=20 > @@ -52,6 +53,7 @@ > #define MAX_TMR 4 > #define VECTOR_BITS 8 > #define MAX_IPI 4 > +#define MAX_MSI 8 > #define VID 0x03 /* MPIC version ID */ >=20 > /* OpenPIC capability flags */ > @@ -62,6 +64,8 @@ > #define OPENPIC_GLB_REG_SIZE 0x10F0 > #define OPENPIC_TMR_REG_START 0x10F0 > #define OPENPIC_TMR_REG_SIZE 0x220 > +#define OPENPIC_MSI_REG_START 0x1600 > +#define OPENPIC_MSI_REG_SIZE 0x200 > #define OPENPIC_SRC_REG_START 0x10000 > #define OPENPIC_SRC_REG_SIZE (MAX_IRQ * 0x20) > #define OPENPIC_CPU_REG_START 0x20000 > @@ -126,6 +130,12 @@ > #define IDR_P1_SHIFT 1 > #define IDR_P0_SHIFT 0 >=20 > +#define MSIIR_OFFSET 0x140 > +#define MSIIR_SRS_SHIFT 29 > +#define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) > +#define MSIIR_IBS_SHIFT 24 > +#define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) FWIW, if you want to model newer MPICs such as on p4080, they have =20 multiple banks of MSIs, so you may not want to hardcode one bank. -Scott=