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Date: Tue, 11 Dec 2012 11:39:51 -0600
From: Scott Wood <scottwood@freescale.com>
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	agraf@suse.de on Tue Dec 11 02:14:42 2012)
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/19] mpic: Unify numbering
	scheme
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To: Alexander Graf <agraf@suse.de>
Cc: "qemu-ppc@nongnu.org List" <qemu-ppc@nongnu.org>, qemu-devel qemu-devel <qemu-devel@nongnu.org>

On 12/11/2012 02:14:42 AM, Alexander Graf wrote:
>=20
>=20
> On 11.12.2012, at 00:34, Scott Wood <scottwood@freescale.com> wrote:
>=20
> > On 12/08/2012 07:44:25 AM, Alexander Graf wrote:
> >> +/* These are available through separate regions, but
> >> +   for simplicity's sake mapped into the same number space */
> >> +#define MPIC_TMR_IRQ      0xf3
> >> +#define MPIC_IPI_IRQ      0xfb
> >
> > Please don't do this, or at least choose different numbers.  0xf3 =20
> is a
> > valid MSI on p4080 (not to mention T4240 which goes beyond 256).
>=20
> Ah, that's where I was wondering myself too. I copied the above logic =20
> from Linux, which maps tmr and ipi to max_irq-x. But I agree that it =20
> sounds off.

Yeah, Linux was buggy and has since been fixed (specifically, we turned =20
on MPIC_LARGE_VECTORS so that max_irq is large enough to not conflict).

-Scott=