From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 5/5] drm/i915: fix gtt space allocated for tiled objects Date: Fri, 04 Jan 2013 19:23:42 +0200 Message-ID: <1357320222.2737.9.camel@localhost> References: <1357317721-6313-1-git-send-email-imre.deak@intel.com> <1357317721-6313-6-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id CA91EE5F50 for ; Fri, 4 Jan 2013 09:23:44 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 2013-01-04 at 17:07 +0000, Chris Wilson wrote: > On Fri, 4 Jan 2013 18:42:00 +0200, Imre Deak wrote: > > The gtt space needed for tiled objects might be bigger than the linear > > size programmed into the correpsonding fence register. For example for > > the following buffer on a Gen5+ HW: > > > > - allocation size: 4096 bytes > > - tiling mode: X tiled > > - stride: 1536 > > > > we need (1536 / 512) * 4096 bytes of gtt space to cover all the pixels > > in the buffer, but at the moment we allocate only 4096. This means that > > any buffer following this tiled buffer in the gtt space will be > > corrupted if pixels belonging to the 2nd and 3rd tiles are written. > > > > Fix this by rounding up the size of the allocated gtt space to the next > > tile row address. The page frames beyond the allocation size will be > > backed by the single gtt scratch page used already elsewhere for similar > > padding. > > > > Note that this is more of a security/robustness problem and not fixing any > > reported issue that I know of. This is because applications will normally > > access only the part of the buffer that is tile row size aligned. > > There should not be any reported issues because all userspace already > allocates up to the end of tile-row and stride should be enforced to be > a multiple of tile-width. So the use of DIV_ROUND_UP implies a > programming error that should have been reported back to userspace > earlier. We can extend that by checking to make sure userspace has > allocated a valid buffer, that is, it has allocated sufficient pages for > the sampler access into the tiled buffer (or reject the set-tiling). > -Chris Ok, I tested this with older UXA that still allocated non-aligned buffers. If that's not the case any more then rejecting set-tiling if it's called on a non tile-row size aligned buffer would work too. --Imre