From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 09/10] drm/i915: print CPU FIFO underruns
Date: Fri, 8 Feb 2013 17:35:20 -0200 [thread overview]
Message-ID: <1360352121-3989-10-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1360352121-3989-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Just like the PCH FIFO underruns, except that there's no place
where we expect it to happen.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 33 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 2 ++
4 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e96d75e..f614ea8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -909,6 +909,8 @@ typedef struct drm_i915_private {
struct work_struct hotplug_work;
bool enable_hotplug_processing;
+ /* Bit 0: pipe A and son on. */
+ u8 ignore_cpu_fifo_underrun;
/* Bit 0: PCH transcoder A and so on. */
u8 ignore_pch_fifo_underrun;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7497589..09bd8d4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -680,6 +680,24 @@ static void err_int_handler(struct drm_device *dev)
if (err_int & ERR_INT_POISON)
DRM_ERROR("Poison interrupt\n");
+ if ((err_int & ERR_INT_FIFO_UNDERRUN_A) &&
+ !(dev_priv->ignore_cpu_fifo_underrun & (1 << PIPE_A))) {
+ DRM_ERROR("Pipe A FIFO underrun\n");
+ dev_priv->ignore_cpu_fifo_underrun |= (1 << PIPE_A);
+ }
+
+ if ((err_int & ERR_INT_FIFO_UNDERRUN_B) &&
+ !(dev_priv->ignore_cpu_fifo_underrun & (1 << PIPE_B))) {
+ DRM_ERROR("Pipe B FIFO underrun\n");
+ dev_priv->ignore_cpu_fifo_underrun |= (1 << PIPE_B);
+ }
+
+ if ((err_int & ERR_INT_FIFO_UNDERRUN_C) &&
+ !(dev_priv->ignore_cpu_fifo_underrun & (1 << PIPE_C))) {
+ DRM_ERROR("Pipe C FIFO underrun\n");
+ dev_priv->ignore_cpu_fifo_underrun |= (1 << PIPE_C);
+ }
+
I915_WRITE(GEN7_ERR_INT, err_int);
}
@@ -901,6 +919,18 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (de_iir & DE_POISON)
DRM_ERROR("Poison interrupt\n");
+ if ((de_iir & DE_PIPEA_FIFO_UNDERRUN) &&
+ !(dev_priv->ignore_cpu_fifo_underrun & (1 << PIPE_A))) {
+ DRM_ERROR("Pipe A FIFO underrun\n");
+ dev_priv->ignore_cpu_fifo_underrun |= (1 << PIPE_A);
+ }
+
+ if ((de_iir & DE_PIPEB_FIFO_UNDERRUN) &&
+ !(dev_priv->ignore_cpu_fifo_underrun & (1 << PIPE_B))) {
+ DRM_ERROR("Pipe B FIFO underrun\n");
+ dev_priv->ignore_cpu_fifo_underrun |= (1 << PIPE_B);
+ }
+
if (de_iir & DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
intel_finish_page_flip_plane(dev, 0);
@@ -2051,7 +2081,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
/* enable kind of interrupts always enabled */
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
- DE_AUX_CHANNEL_A | DE_POISON;
+ DE_AUX_CHANNEL_A | DE_POISON |
+ DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
u32 render_irqs;
dev_priv->irq_mask = ~display_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d565bd7..c0db8b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,6 +521,9 @@
#define GEN7_ERR_INT 0x44040
#define ERR_INT_POISON (1<<31)
#define ERR_INT_MMIO_UNCLAIMED (1<<13)
+#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
+#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
+#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
#define FPGA_DBG 0x42300
#define FPGA_DBG_RM_NOCLAIM (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 67bfb58..030a8d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3275,6 +3275,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_crtc->active = true;
+ dev_priv->ignore_cpu_fifo_underrun &= ~(1 << pipe);
dev_priv->ignore_pch_fifo_underrun &= ~(1 << pipe);
intel_update_watermarks(dev);
@@ -3372,6 +3373,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
is_pch_port = haswell_crtc_driving_pch(crtc);
+ dev_priv->ignore_cpu_fifo_underrun &= ~(1 << pipe);
if (is_pch_port)
dev_priv->ignore_pch_fifo_underrun &= ~(1 << TRANSCODER_A);
--
1.7.10.4
next prev parent reply other threads:[~2013-02-08 19:36 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-08 19:35 [PATCH 00/10] Display error reporting Paulo Zanoni
2013-02-08 19:35 ` [PATCH 01/10] drm/i915: drm/i915: create macros for the "unclaimed register" checks Paulo Zanoni
2013-02-18 18:11 ` Daniel Vetter
2013-02-08 19:35 ` [PATCH 02/10] drm/i915: use FPGA_DBG " Paulo Zanoni
2013-02-08 19:35 ` [PATCH 03/10] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init Paulo Zanoni
2013-02-09 17:19 ` Ben Widawsky
2013-02-14 20:26 ` Paulo Zanoni
2013-02-15 4:07 ` Ben Widawsky
2013-02-08 19:35 ` [PATCH 04/10] drm/i915: add ibx_irq_postinstall Paulo Zanoni
2013-02-09 17:27 ` Ben Widawsky
2013-02-09 19:07 ` Daniel Vetter
2013-02-08 19:35 ` [PATCH 05/10] drm/i915: also disable south interrupts when handling them Paulo Zanoni
2013-02-09 19:29 ` Daniel Vetter
2013-02-20 20:06 ` Paulo Zanoni
2013-02-20 20:24 ` Daniel Vetter
2013-02-08 19:35 ` [PATCH 06/10] drm/i915: print PCH poison interrupts Paulo Zanoni
2013-02-08 19:35 ` [PATCH 07/10] drm/i915: print Gen5+ CPU " Paulo Zanoni
2013-02-08 19:42 ` Jesse Barnes
2013-02-08 19:54 ` Paulo Zanoni
2013-02-08 20:01 ` Jesse Barnes
2013-02-09 17:30 ` Ben Widawsky
2013-02-14 20:35 ` Paulo Zanoni
2013-02-15 4:05 ` Ben Widawsky
2013-02-08 19:35 ` [PATCH 08/10] drm/i915: print PCH FIFO underrun interrupts Paulo Zanoni
2013-02-09 19:43 ` Daniel Vetter
2013-02-14 20:53 ` Paulo Zanoni
2013-02-14 21:13 ` Daniel Vetter
2013-02-14 21:32 ` Paulo Zanoni
2013-02-08 19:35 ` Paulo Zanoni [this message]
2013-02-08 19:35 ` [PATCH 10/10] drm/i915: also POSTING_READ(DEIER) on ivybridge_irq_handler Paulo Zanoni
2013-02-09 17:34 ` Ben Widawsky
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1360352121-3989-10-git-send-email-przanoni@gmail.com \
--to=przanoni@gmail.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=paulo.r.zanoni@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.