From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 10/10] drm/i915: also POSTING_READ(DEIER) on ivybridge_irq_handler Date: Fri, 8 Feb 2013 17:35:21 -0200 Message-ID: <1360352121-3989-11-git-send-email-przanoni@gmail.com> References: <1360352121-3989-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gg0-f182.google.com (mail-gg0-f182.google.com [209.85.161.182]) by gabe.freedesktop.org (Postfix) with ESMTP id 91F3EE62CC for ; Fri, 8 Feb 2013 11:36:14 -0800 (PST) Received: by mail-gg0-f182.google.com with SMTP id d1so490956ggn.27 for ; Fri, 08 Feb 2013 11:36:14 -0800 (PST) In-Reply-To: <1360352121-3989-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This is already done on ironlake_irq_handler. We want to make sure the interrupts are disabled before we check any of the other interrupt registers. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 09bd8d4..e9a6ade 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -786,6 +786,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg) /* disable master interrupt before clearing iir */ de_ier = I915_READ(DEIER); I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); + POSTING_READ(DEIER); /* On Haswell, also mask ERR_INT because we don't want to risk * generating "unclaimed register" interrupts from inside the interrupt -- 1.7.10.4