From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Michael Neuling <mikey@neuling.org>
Cc: linuxppc-dev@lists.ozlabs.org, Ian Munsie <imunsie@au1.ibm.com>
Subject: Re: [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition
Date: Tue, 05 Mar 2013 16:09:58 +1100 [thread overview]
Message-ID: <1362460198.21357.47.camel@pasglop> (raw)
In-Reply-To: <1362390402-17725-3-git-send-email-mikey@neuling.org>
On Mon, 2013-03-04 at 20:46 +1100, Michael Neuling wrote:
> Also harmonise TAR bit definition too.
Same, expand accronyms, minimum blurb about what these are about (not a
long explanation, just so that when I come out of the blue I can at
least connect it to something that makes sense :-)
Cheers,
Ben.
next prev parent reply other threads:[~2013-03-05 5:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-04 9:46 [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling
2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling
2013-03-05 5:06 ` Benjamin Herrenschmidt
2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling
2013-03-05 5:45 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs Michael Neuling
2013-03-05 5:45 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling
2013-03-05 5:45 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling
2013-03-04 9:46 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling
2013-03-05 5:09 ` Benjamin Herrenschmidt [this message]
2013-03-04 9:46 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling
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