diff for duplicates of <1363713985.16671.12@snotra> diff --git a/a/1.txt b/N1/1.txt index 7ef9599..0b2e521 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,11 +3,11 @@ On 03/19/2013 12:17:11 PM, Mihai Caraman wrote: > index 66b6e31..b77b855 100644 > --- a/arch/powerpc/kvm/e500_mmu.c > +++ b/arch/powerpc/kvm/e500_mmu.c -> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu +> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu =20 > *vcpu, struct kvm_sregs *sregs) > return 0; > } -> +>=20 > +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id, > + union kvmppc_one_reg *val) @@ -16,61 +16,62 @@ s/500/e500/ > +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id, > + union kvmppc_one_reg *val) > +{ -> + int r = 0; +> + int r =3D 0; > + long int i; > + > + switch (id) { > + case KVM_REG_PPC_MAS0: -> + vcpu->arch.shared->mas0 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas0 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MAS1: -> + vcpu->arch.shared->mas1 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas1 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MAS2: -> + vcpu->arch.shared->mas2 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas2 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MAS7_3: -> + vcpu->arch.shared->mas7_3 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MAS4: -> + vcpu->arch.shared->mas4 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas4 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MAS6: -> + vcpu->arch.shared->mas6 = set_reg_val(id, *val); +> + vcpu->arch.shared->mas6 =3D set_reg_val(id, *val); > + break; > + case KVM_REG_PPC_MMUCFG: { -> + u32 mmucfg = set_reg_val(id, *val); -> + vcpu->arch.mmucfg = mmucfg & ~MMUCFG_LPIDSIZE; +> + u32 mmucfg =3D set_reg_val(id, *val); +> + vcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE; > + break; > + } -Do we really want to allow arbitrary MMUCFG changes? It won't +Do we really want to allow arbitrary MMUCFG changes? It won't =20 magically make us able to support larger RAs, PIDs, different MAVN, etc. > + case KVM_REG_PPC_TLB0CFG: > + case KVM_REG_PPC_TLB1CFG: > + case KVM_REG_PPC_TLB2CFG: > + case KVM_REG_PPC_TLB3CFG: { -> + u32 tlbncfg = set_reg_val(id, -> *val); -> + u32 geometry_mask = TLBnCFG_N_ENTRY | TLBnCFG_ASSOC; -> + i = id - KVM_REG_PPC_TLB0CFG; +> + u32 tlbncfg =3D set_reg_val(id, =20 +> *val); =09 +> + u32 geometry_mask =3D TLBnCFG_N_ENTRY | TLBnCFG_ASSOC; +> + i =3D id - KVM_REG_PPC_TLB0CFG; > + -> + /* MMU geometry (way/size) can be set only using SW_TLB +> + /* MMU geometry (way/size) can be set only using SW_TLB =20 > */ -> + if ((vcpu->arch.tlbcfg[i] & geometry_mask) !> + (tlbncfg & geometry_mask)) -> + r = -EINVAL; +> + if ((vcpu->arch.tlbcfg[i] & geometry_mask) !=3D +> + (tlbncfg & geometry_mask)) +> + r =3D -EINVAL; > + -> + vcpu->arch.tlbcfg[i] = set_reg_val(id, *val); +> + vcpu->arch.tlbcfg[i] =3D set_reg_val(id, *val); > + break; > + } -Likewise -- just because QEMU sets a bit here doesn't mean KVM can +Likewise -- just because QEMU sets a bit here doesn't mean KVM can =20 support it. -I thought the initial plan for setting these config registers was to -accept it if it exactly matches what KVM already has, and give an error -otherwise -- thus allowing for the possibliity of accepting certain +I thought the initial plan for setting these config registers was to =20 +accept it if it exactly matches what KVM already has, and give an error =20 +otherwise -- thus allowing for the possibliity of accepting certain =20 specific updates in the future. --Scott +-Scott= diff --git a/a/content_digest b/N1/content_digest index a26409b..468faaf 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,12 @@ "ref\01363713431-27926-1-git-send-email-mihai.caraman@freescale.com\0" "From\0Scott Wood <scottwood@freescale.com>\0" "Subject\0Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG\0" - "Date\0Tue, 19 Mar 2013 17:26:25 +0000\0" + "Date\0Tue, 19 Mar 2013 12:26:25 -0500\0" "To\0Mihai Caraman <mihai.caraman@freescale.com>\0" - "Cc\0kvm-ppc@vger.kernel.org" - Mihai Caraman <mihai.caraman@freescale.com> + "Cc\0Mihai Caraman <mihai.caraman@freescale.com>" linuxppc-dev@lists.ozlabs.org - " kvm@vger.kernel.org\0" + kvm@vger.kernel.org + " kvm-ppc@vger.kernel.org\0" "\00:1\0" "b\0" "On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:\n" @@ -14,11 +14,11 @@ "> index 66b6e31..b77b855 100644\n" "> --- a/arch/powerpc/kvm/e500_mmu.c\n" "> +++ b/arch/powerpc/kvm/e500_mmu.c\n" - "> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu \n" + "> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu =20\n" "> *vcpu, struct kvm_sregs *sregs)\n" "> \treturn 0;\n" "> }\n" - "> \n" + ">=20\n" "> +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,\n" "> +\t\t\t\tunion kvmppc_one_reg *val)\n" "\n" @@ -27,63 +27,64 @@ "> +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,\n" "> +\t\t\t union kvmppc_one_reg *val)\n" "> +{\n" - "> +\tint r = 0;\n" + "> +\tint r =3D 0;\n" "> +\tlong int i;\n" "> +\n" "> +\tswitch (id) {\n" "> +\tcase KVM_REG_PPC_MAS0:\n" - "> +\t\tvcpu->arch.shared->mas0 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas0 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MAS1:\n" - "> +\t\tvcpu->arch.shared->mas1 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas1 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MAS2:\n" - "> +\t\tvcpu->arch.shared->mas2 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas2 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MAS7_3:\n" - "> +\t\tvcpu->arch.shared->mas7_3 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MAS4:\n" - "> +\t\tvcpu->arch.shared->mas4 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas4 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MAS6:\n" - "> +\t\tvcpu->arch.shared->mas6 = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.shared->mas6 =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\tcase KVM_REG_PPC_MMUCFG: {\n" - "> +\t\tu32 mmucfg = set_reg_val(id, *val);\n" - "> +\t\tvcpu->arch.mmucfg = mmucfg & ~MMUCFG_LPIDSIZE;\n" + "> +\t\tu32 mmucfg =3D set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE;\n" "> +\t\tbreak;\n" "> +\t}\n" "\n" - "Do we really want to allow arbitrary MMUCFG changes? It won't \n" + "Do we really want to allow arbitrary MMUCFG changes? It won't =20\n" "magically make us able to support larger RAs, PIDs, different MAVN, etc.\n" "\n" "> +\tcase KVM_REG_PPC_TLB0CFG:\n" "> +\tcase KVM_REG_PPC_TLB1CFG:\n" "> +\tcase KVM_REG_PPC_TLB2CFG:\n" "> +\tcase KVM_REG_PPC_TLB3CFG: {\n" - "> +\t\tu32 tlbncfg = set_reg_val(id, \n" - "> *val);\t\t\t\t\n" - "> +\t\tu32 geometry_mask = TLBnCFG_N_ENTRY | TLBnCFG_ASSOC;\n" - "> +\t\ti = id - KVM_REG_PPC_TLB0CFG;\n" + "> +\t\tu32 tlbncfg =3D set_reg_val(id, =20\n" + "> *val);\t\t\t=09\n" + "> +\t\tu32 geometry_mask =3D TLBnCFG_N_ENTRY | TLBnCFG_ASSOC;\n" + "> +\t\ti =3D id - KVM_REG_PPC_TLB0CFG;\n" "> +\n" - "> +\t\t/* MMU geometry (way/size) can be set only using SW_TLB \n" + "> +\t\t/* MMU geometry (way/size) can be set only using SW_TLB =20\n" "> */\n" - "> +\t\tif ((vcpu->arch.tlbcfg[i] & geometry_mask) !> +\t\t (tlbncfg & geometry_mask))\n" - "> +\t\t\tr = -EINVAL;\n" + "> +\t\tif ((vcpu->arch.tlbcfg[i] & geometry_mask) !=3D\n" + "> +\t\t (tlbncfg & geometry_mask))\n" + "> +\t\t\tr =3D -EINVAL;\n" "> +\n" - "> +\t\tvcpu->arch.tlbcfg[i] = set_reg_val(id, *val);\n" + "> +\t\tvcpu->arch.tlbcfg[i] =3D set_reg_val(id, *val);\n" "> +\t\tbreak;\n" "> +\t}\n" "\n" - "Likewise -- just because QEMU sets a bit here doesn't mean KVM can \n" + "Likewise -- just because QEMU sets a bit here doesn't mean KVM can =20\n" "support it.\n" "\n" - "I thought the initial plan for setting these config registers was to \n" - "accept it if it exactly matches what KVM already has, and give an error \n" - "otherwise -- thus allowing for the possibliity of accepting certain \n" + "I thought the initial plan for setting these config registers was to =20\n" + "accept it if it exactly matches what KVM already has, and give an error =20\n" + "otherwise -- thus allowing for the possibliity of accepting certain =20\n" "specific updates in the future.\n" "\n" - -Scott + -Scott= -ca1af13d38d04eb7a98ccb74a100b9e1fc5f55963fcbd90a4e49e4bac91a3cda +6707488547fb4e062d36e718008f17704010f4cdfb3c87921437c415aadfb26e
diff --git a/a/1.txt b/N2/1.txt index 7ef9599..b0dc43d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -58,7 +58,8 @@ magically make us able to support larger RAs, PIDs, different MAVN, etc. > + > + /* MMU geometry (way/size) can be set only using SW_TLB > */ -> + if ((vcpu->arch.tlbcfg[i] & geometry_mask) !> + (tlbncfg & geometry_mask)) +> + if ((vcpu->arch.tlbcfg[i] & geometry_mask) != +> + (tlbncfg & geometry_mask)) > + r = -EINVAL; > + > + vcpu->arch.tlbcfg[i] = set_reg_val(id, *val); diff --git a/a/content_digest b/N2/content_digest index a26409b..33c4ae6 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,12 @@ "ref\01363713431-27926-1-git-send-email-mihai.caraman@freescale.com\0" "From\0Scott Wood <scottwood@freescale.com>\0" "Subject\0Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG\0" - "Date\0Tue, 19 Mar 2013 17:26:25 +0000\0" + "Date\0Tue, 19 Mar 2013 12:26:25 -0500\0" "To\0Mihai Caraman <mihai.caraman@freescale.com>\0" - "Cc\0kvm-ppc@vger.kernel.org" + "Cc\0<kvm-ppc@vger.kernel.org>" Mihai Caraman <mihai.caraman@freescale.com> - linuxppc-dev@lists.ozlabs.org - " kvm@vger.kernel.org\0" + <linuxppc-dev@lists.ozlabs.org> + " <kvm@vger.kernel.org>\0" "\00:1\0" "b\0" "On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:\n" @@ -69,7 +69,8 @@ "> +\n" "> +\t\t/* MMU geometry (way/size) can be set only using SW_TLB \n" "> */\n" - "> +\t\tif ((vcpu->arch.tlbcfg[i] & geometry_mask) !> +\t\t (tlbncfg & geometry_mask))\n" + "> +\t\tif ((vcpu->arch.tlbcfg[i] & geometry_mask) !=\n" + "> +\t\t (tlbncfg & geometry_mask))\n" "> +\t\t\tr = -EINVAL;\n" "> +\n" "> +\t\tvcpu->arch.tlbcfg[i] = set_reg_val(id, *val);\n" @@ -86,4 +87,4 @@ "\n" -Scott -ca1af13d38d04eb7a98ccb74a100b9e1fc5f55963fcbd90a4e49e4bac91a3cda +e2433a815f097e486d9e8923becd3ebb40574b700b410e92068ca30aae55ab66
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