From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 11/13] drm/i915: add clock_get for ironlake+ Date: Wed, 20 Mar 2013 14:48:22 +0200 Message-ID: <1363783702.13528.33.camel@intelbox> References: <1361309508-4901-1-git-send-email-jbarnes@virtuousgeek.org> <1361309508-4901-12-git-send-email-jbarnes@virtuousgeek.org> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id BAE85E5DB2 for ; Wed, 20 Mar 2013 05:48:24 -0700 (PDT) In-Reply-To: <1361309508-4901-12-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 2013-02-19 at 13:31 -0800, Jesse Barnes wrote: > Turns out it's easy to get the clock, though it may correspond to a > potential pfit mode. In that case, we may still be able to flip if > we can get the native mode params somehow. This should be merged to 6/13. > > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++++++++--- > 1 file changed, 23 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 91660b1..861af1a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6771,6 +6771,27 @@ static bool i9xx_crtc_get_mode(struct drm_crtc *crtc, > return true; > } > > +static int ironlake_crtc_clock_get(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = crtc->dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; > + int clock; > + u32 link_m; > + > + /* > + * PCH platforms make this easy: we can just use the LINK_M1 reg. > + * Note: this may be the pixel clock for a fitted mode, in which > + * case it won't match the native mode clock. That means we won't be > + * able to do a simple flip in the fastboot case. > + */ > + link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder)); > + > + clock = link_m; > + > + return clock; > +} Could be simply return I915_READ(PIPE_LINK_M1(cpu_transcoder)); > + > static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, > struct drm_display_mode *mode) > { > @@ -6797,12 +6818,11 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, > mode->vsync_start = (tmp & 0xffff) + 1; > mode->vsync_end = ((tmp & 0xffff0000) >> 16) + 1; > > - //mode->clock = i9xx_crtc_clock_get(crtc); > - //mode->clock = 69300; > + mode->clock = ironlake_crtc_clock_get(crtc); > > drm_mode_set_name(mode); > > - return false; /* XXX mode->clock unset */ > + return true; > } > > static __maybe_unused bool no_crtc_get_mode(struct drm_crtc *crtc,