From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UL0Gc-0000Jt-9m for qemu-devel@nongnu.org; Wed, 27 Mar 2013 20:00:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UL0Gb-0004FU-BQ for qemu-devel@nongnu.org; Wed, 27 Mar 2013 20:00:30 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:56731) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UL0Gb-0004DV-50 for qemu-devel@nongnu.org; Wed, 27 Mar 2013 20:00:29 -0400 From: Aurelien Jarno Date: Thu, 28 Mar 2013 01:00:08 +0100 Message-Id: <1364428811-8226-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 0/3] target-i386: add PCLMULQDQ and AES-NI instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno This patch series adds the PCLMULQDQ and AES-NI instructions to the x86 emulation. Along with the SSE4.1 and SSE4.2 series, this brings the instructions emulation to the level of a Westmere CPU. It has been tested with the valgrind testsuite and with the kernel autotest. Aurelien Jarno (3): target-i386: add pclmulqdq instruction target-i386: enable PCLMULQDQ on Westmere CPU target-i386: add AES-NI instructions target-i386/cpu.c | 19 ++-- target-i386/ops_sse.h | 212 ++++++++++++++++++++++++++++++++++++++++++ target-i386/ops_sse_header.h | 11 +++ target-i386/translate.c | 10 ++ 4 files changed, 242 insertions(+), 10 deletions(-) -- 1.7.10.4