From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48875) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULRZr-00061u-NR for qemu-devel@nongnu.org; Fri, 29 Mar 2013 01:10:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULRZq-0003hW-8t for qemu-devel@nongnu.org; Fri, 29 Mar 2013 01:10:11 -0400 Received: from mail-ie0-x22c.google.com ([2607:f8b0:4001:c03::22c]:34181) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULRZq-0003fL-53 for qemu-devel@nongnu.org; Fri, 29 Mar 2013 01:10:10 -0400 Received: by mail-ie0-f172.google.com with SMTP id c10so243486ieb.3 for ; Thu, 28 Mar 2013 22:10:08 -0700 (PDT) Date: Fri, 29 Mar 2013 00:10:04 -0500 From: Rob Landley References: <1362017554-1260-1-git-send-email-hpa@zytor.com> <20130328191533.GA23069@ohm.aurel32.net> <5154A41B.2030609@zytor.com> In-Reply-To: <5154A41B.2030609@zytor.com> (from hpa@zytor.com on Thu Mar 28 15:12:11 2013) Message-Id: <1364533804.18069.9@driftwood> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; DelSp=Yes; Format=Flowed Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC PATCH 1/3] target-i386: Add 486sx, old486, and old486sx CPU models List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "H. Peter Anvin" Cc: qemu-devel@nongnu.org, Aurelien Jarno On 03/28/2013 03:12:11 PM, H. Peter Anvin wrote: > On 03/28/2013 12:15 PM, Aurelien Jarno wrote: > > > > This really looks like Linux kernel specific. I haven't been able to > > test on a real machine, but the documentation I have found suggest =20 > that > > without and x87 FPU, the FPU instructions are simply ignored. The =20 > common > > way to detect an FPU is therefore to initialize registers to a given > > value, run fnstsw and fnstcw instructions with the register in =20 > arguments > > and see if they have been modified. > > > > The Linux kernel indeed set the initial value of these registers to > > 0xffff, but I am not sure all codes are doing the same. > > > > For me it looks like better to skip such instructions directly in > > translate.c. As a bonus it seems easy to do that for all FPU > > instructions. > > >=20 > It might have been (and this is from memory, so don't take it for > anything) that the register form receives 0xffff, but the memory form =20 > is > ignored. Speaking of which, Solar Designer recently found a bug where pentium 3 =20 silently ignores the 66 prefix that later became SSE2, and thus the =20 code ran but produced the wrong result: https://twitter.com/solardiz/status/316204216962142209 https://twitter.com/solardiz/status/316207184134410240 But this isn't what QEMU does: https://twitter.com/solardiz/status/316944417871245313 Rob=