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Date: Tue, 2 Apr 2013 14:19:01 -0500
From: Scott Wood <scottwood@freescale.com>
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree
 files for B4860 and B4420
To: Shaveta Leekha <shaveta@freescale.com>
References: <1364886968-9634-1-git-send-email-shaveta@freescale.com>
In-Reply-To: <1364886968-9634-1-git-send-email-shaveta@freescale.com> (from
 shaveta@freescale.com on Tue Apr  2 02:16:05 2013)
Message-ID: <1364930341.24520.15@snotra>
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Cc: Zhao Chenhui <chenhui.zhao@freescale.com>,
 Tang Yuantian <Yuantian.Tang@freescale.com>,
 Shaveta Leekha <shaveta@freescale.com>, Vakul Garg <vakul@freescale.com>,
 Minghuan Lian <Minghuan.Lian@freescale.com>,
 Andy Fleming <afleming@freescale.com>,
 Ramneek Mehresh <ramneek.mehresh@freescale.com>,
 Varun Sethi <Varun.Sethi@freescale.com>, linuxppc-dev@lists.ozlabs.org
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On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> +/ {
> +	compatible =3D "fsl,B4860";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu2: PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu3: PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};

The unit addresses need to match "reg".

-Scott=