From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UPZuF-0001MZ-5M for qemu-devel@nongnu.org; Tue, 09 Apr 2013 10:52:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UPZu6-0008Iz-HH for qemu-devel@nongnu.org; Tue, 09 Apr 2013 10:52:19 -0400 Received: from cantor2.suse.de ([195.135.220.15]:60049 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UPZu6-00080V-3Z for qemu-devel@nongnu.org; Tue, 09 Apr 2013 10:52:10 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 9 Apr 2013 16:51:24 +0200 Message-Id: <1365519084-4229-3-git-send-email-afaerber@suse.de> In-Reply-To: <1365519084-4229-1-git-send-email-afaerber@suse.de> References: <1365519084-4229-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu 2/2] sh7750: Change cpu field type to SuperHCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , aurelien@aurel32.net This brings us a step closer to QOM'ified SH7750 SoC and fixes b350ab75 (target-sh4: Move PVR/PRR/CVR into SuperHCPUClass) assuming SuperHCPU type for SUPERH_CPU_GET_CLASS(). Fix Coding Style issues while at it (indentation, braces). Reported-by: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- hw/sh4/r2d.c | 2 +- hw/sh4/sh7750.c | 91 +++++++++++++++++++++++++++--------------------= ------ hw/sh4/shix.c | 8 ++--- include/hw/sh4/sh.h | 2 +- 4 files changed, 52 insertions(+), 51 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 256a58c..fe82bd62 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -258,7 +258,7 @@ static void r2d_init(QEMUMachineInitArgs *args) vmstate_register_ram_global(sdram); memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); /* Register peripherals */ - s =3D sh7750_init(env, address_space_mem); + s =3D sh7750_init(cpu, address_space_mem); irq =3D r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); =20 dev =3D qdev_create(NULL, "sh_pci"); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 2218b9c..03e8bd1 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -44,7 +44,7 @@ typedef struct SH7750State { MemoryRegion iomem_ffc; MemoryRegion mmct_iomem; /* CPU */ - CPUSH4State *cpu; + SuperHCPU *cpu; /* Peripheral frequency in Hz */ uint32_t periph_freq; /* SDRAM controller */ @@ -79,7 +79,7 @@ typedef struct SH7750State { =20 static inline int has_bcr3_and_bcr4(SH7750State * s) { - return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4); + return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; } /********************************************************************** I/O ports @@ -271,21 +271,21 @@ static uint32_t sh7750_mem_readl(void *opaque, hwad= dr addr) ignore_access("long read", addr); return 0; case SH7750_MMUCR_A7: - return s->cpu->mmucr; + return s->cpu->env.mmucr; case SH7750_PTEH_A7: - return s->cpu->pteh; + return s->cpu->env.pteh; case SH7750_PTEL_A7: - return s->cpu->ptel; + return s->cpu->env.ptel; case SH7750_TTB_A7: - return s->cpu->ttb; + return s->cpu->env.ttb; case SH7750_TEA_A7: - return s->cpu->tea; + return s->cpu->env.tea; case SH7750_TRA_A7: - return s->cpu->tra; + return s->cpu->env.tra; case SH7750_EXPEVT_A7: - return s->cpu->expevt; + return s->cpu->env.expevt; case SH7750_INTEVT_A7: - return s->cpu->intevt; + return s->cpu->env.intevt; case SH7750_CCR_A7: return s->ccr; case 0x1f000030: /* Processor version */ @@ -409,37 +409,38 @@ static void sh7750_mem_writel(void *opaque, hwaddr = addr, return; case SH7750_MMUCR_A7: if (mem_value & MMUCR_TI) { - cpu_sh4_invalidate_tlb(s->cpu); + cpu_sh4_invalidate_tlb(&s->cpu->env); } - s->cpu->mmucr =3D mem_value & ~MMUCR_TI; + s->cpu->env.mmucr =3D mem_value & ~MMUCR_TI; return; case SH7750_PTEH_A7: /* If asid changes, clear all registered tlb entries. */ - if ((s->cpu->pteh & 0xff) !=3D (mem_value & 0xff)) - tlb_flush(s->cpu, 1); - s->cpu->pteh =3D mem_value; - return; + if ((s->cpu->env.pteh & 0xff) !=3D (mem_value & 0xff)) { + tlb_flush(&s->cpu->env, 1); + } + s->cpu->env.pteh =3D mem_value; + return; case SH7750_PTEL_A7: - s->cpu->ptel =3D mem_value; - return; + s->cpu->env.ptel =3D mem_value; + return; case SH7750_PTEA_A7: - s->cpu->ptea =3D mem_value & 0x0000000f; - return; + s->cpu->env.ptea =3D mem_value & 0x0000000f; + return; case SH7750_TTB_A7: - s->cpu->ttb =3D mem_value; - return; + s->cpu->env.ttb =3D mem_value; + return; case SH7750_TEA_A7: - s->cpu->tea =3D mem_value; - return; + s->cpu->env.tea =3D mem_value; + return; case SH7750_TRA_A7: - s->cpu->tra =3D mem_value & 0x000007ff; - return; + s->cpu->env.tra =3D mem_value & 0x000007ff; + return; case SH7750_EXPEVT_A7: - s->cpu->expevt =3D mem_value & 0x000007ff; - return; + s->cpu->env.expevt =3D mem_value & 0x000007ff; + return; case SH7750_INTEVT_A7: - s->cpu->intevt =3D mem_value & 0x000007ff; - return; + s->cpu->env.intevt =3D mem_value & 0x000007ff; + return; case SH7750_CCR_A7: s->ccr =3D mem_value; return; @@ -651,20 +652,20 @@ static uint64_t sh7750_mmct_read(void *opaque, hwad= dr addr, /* do nothing */ break; case MM_ITLB_ADDR: - ret =3D cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); break; case MM_ITLB_DATA: - ret =3D cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); break; case MM_OCACHE_ADDR: case MM_OCACHE_DATA: /* do nothing */ break; case MM_UTLB_ADDR: - ret =3D cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); break; case MM_UTLB_DATA: - ret =3D cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); + ret =3D cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); break; default: abort(); @@ -694,10 +695,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr = addr, /* do nothing */ break; case MM_ITLB_ADDR: - cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); break; case MM_ITLB_DATA: - cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); abort(); break; case MM_OCACHE_ADDR: @@ -705,10 +706,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr = addr, /* do nothing */ break; case MM_UTLB_ADDR: - cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); break; case MM_UTLB_DATA: - cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); + cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); break; default: abort(); @@ -722,7 +723,7 @@ static const MemoryRegionOps sh7750_mmct_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) +SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; =20 @@ -768,7 +769,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryReg= ion *sysmem) _INTC_ARRAY(vectors), _INTC_ARRAY(groups)); =20 - cpu->intc_handle =3D &s->intc; + cpu->env.intc_handle =3D &s->intc; =20 sh_serial_init(sysmem, 0x1fe00000, 0, s->periph_freq, serial_hds[0], @@ -794,19 +795,19 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryR= egion *sysmem) s->intc.irqs[TMU2_TUNI], s->intc.irqs[TMU2_TICPI]); =20 - if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { + if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) = { sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_dma4), _INTC_ARRAY(groups_dma4)); } =20 - if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { + if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_dma8), _INTC_ARRAY(groups_dma8)); } =20 - if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { + if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R))= { sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_tmu34), NULL, 0); @@ -816,13 +817,13 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryR= egion *sysmem) NULL, NULL); } =20 - if (cpu->id & (SH_CPU_SH7751_ALL)) { + if (cpu->env.id & (SH_CPU_SH7751_ALL)) { sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_pci), _INTC_ARRAY(groups_pci)); } =20 - if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL))= { + if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_A= LL)) { sh_intc_register_sources(&s->intc, _INTC_ARRAY(vectors_irlm), NULL, 0); diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index f5cfef9..ffac621 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -41,7 +41,7 @@ static void shix_init(QEMUMachineInitArgs *args) { const char *cpu_model =3D args->cpu_model; int ret; - CPUSH4State *env; + SuperHCPU *cpu; struct SH7750State *s; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *rom =3D g_new(MemoryRegion, 1); @@ -51,8 +51,8 @@ static void shix_init(QEMUMachineInitArgs *args) cpu_model =3D "any"; =20 printf("Initializing CPU\n"); - env =3D cpu_init(cpu_model); - if (env =3D=3D NULL) { + cpu =3D cpu_sh4_init(cpu_model); + if (cpu =3D=3D NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -85,7 +85,7 @@ static void shix_init(QEMUMachineInitArgs *args) } =20 /* Register peripherals */ - s =3D sh7750_init(env, sysmem); + s =3D sh7750_init(cpu, sysmem); /* XXXXX Check success */ tc58128_init(s, "shix_linux_nand.bin", NULL); fprintf(stderr, "initialization terminated\n"); diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 87c378f..e61de9a 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -11,7 +11,7 @@ struct SH7750State; struct MemoryRegion; =20 -struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *= sysmem); +struct SH7750State *sh7750_init(SuperHCPU *cpu, struct MemoryRegion *sys= mem); =20 typedef struct { /* The callback will be triggered if any of the designated lines cha= nge */ --=20 1.8.1.4