From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URHw1-00075M-EF for qemu-devel@nongnu.org; Sun, 14 Apr 2013 04:05:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URHvz-0003wP-Qy for qemu-devel@nongnu.org; Sun, 14 Apr 2013 04:05:13 -0400 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:53839) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URHvz-0003vj-5m for qemu-devel@nongnu.org; Sun, 14 Apr 2013 04:05:11 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 14 Apr 2013 10:05:56 +0200 Message-Id: <1365926760-5803-4-git-send-email-hpoussin@reactos.org> In-Reply-To: <1365926760-5803-1-git-send-email-hpoussin@reactos.org> References: <1365926760-5803-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC v2 3/7] m48t59: register a QOM type for each nvram type we support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= As m48t59 devices can only be created with m48t59_init() or m48t59_init_i= sa(), we know exactly which nvram types are required. Register only those three types. Remove .model and .size properties as they can be infered from nvram name= . Remove .io_base ISA address port as m48t59_init_isa() is always called wi= th ioport 0x74. Signed-off-by: Herv=C3=A9 Poussineau --- hw/timer/m48t59.c | 187 ++++++++++++++++++++++++++++++++++++-----------= ------ 1 file changed, 126 insertions(+), 61 deletions(-) diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index 41022f2..29ec462 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -43,6 +43,13 @@ * PPC platform there is also a nvram lock function. */ =20 +typedef struct M48txxInfo { + const char *isa_name; + const char *sysbus_name; + uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ + uint32_t size; +} M48txxInfo; + /* * Chipset docs: * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf @@ -54,7 +61,6 @@ struct M48t59State { /* Hardware parameters */ qemu_irq IRQ; MemoryRegion iomem; - uint32_t io_base; uint32_t size; /* RTC management */ time_t time_offset; @@ -78,12 +84,39 @@ typedef struct M48t59ISAState { MemoryRegion io; } M48t59ISAState; =20 +typedef struct M48txxISADeviceClass { + ISADeviceClass parent_class; + M48txxInfo info; +} M48txxISADeviceClass; + typedef struct M48t59SysBusState { SysBusDevice busdev; M48t59State state; MemoryRegion io; } M48t59SysBusState; =20 +typedef struct M48txxSysBusDeviceClass { + SysBusDeviceClass parent_class; + M48txxInfo info; +} M48txxSysBusDeviceClass; + +static M48txxInfo m48txx_info[] =3D { + { + .sysbus_name =3D "m48t02", + .model =3D 2, + .size =3D 0x800, + },{ + .sysbus_name =3D "m48t08", + .model =3D 8, + .size =3D 0x2000, + },{ + .isa_name =3D "m48t59_isa", + .model =3D 59, + .size =3D 0x2000, + } +}; + + /* Fake timer functions */ =20 /* Alarm management */ @@ -640,25 +673,34 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_b= ase, SysBusDevice *s; M48t59SysBusState *d; M48t59State *state; + int i; =20 - dev =3D qdev_create(NULL, "m48t59"); - qdev_prop_set_uint32(dev, "model", model); - qdev_prop_set_uint32(dev, "size", size); - qdev_prop_set_uint32(dev, "io_base", io_base); - qdev_init_nofail(dev); - s =3D SYS_BUS_DEVICE(dev); - d =3D FROM_SYSBUS(M48t59SysBusState, s); - state =3D &d->state; - sysbus_connect_irq(s, 0, IRQ); - memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); - if (io_base !=3D 0) { - memory_region_add_subregion(get_system_io(), io_base, &d->io); - } - if (mem_base !=3D 0) { - sysbus_mmio_map(s, 0, mem_base); + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (!m48txx_info[i].sysbus_name || + m48txx_info[i].size !=3D size || + m48txx_info[i].model !=3D model) { + continue; + } + + dev =3D qdev_create(NULL, m48txx_info[i].sysbus_name); + qdev_init_nofail(dev); + s =3D SYS_BUS_DEVICE(dev); + d =3D FROM_SYSBUS(M48t59SysBusState, s); + state =3D &d->state; + sysbus_connect_irq(s, 0, IRQ); + memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4= ); + if (io_base !=3D 0) { + memory_region_add_subregion(get_system_io(), io_base, &d->io= ); + } + if (mem_base !=3D 0) { + sysbus_mmio_map(s, 0, mem_base); + } + + return state; } =20 - return state; + assert(false); + return NULL; } =20 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t siz= e, @@ -667,16 +709,27 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t = io_base, uint16_t size, M48t59ISAState *d; ISADevice *dev; M48t59State *s; + int i; + + assert(io_base =3D=3D 0x74); + + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (!m48txx_info[i].isa_name || + m48txx_info[i].size !=3D size || + m48txx_info[i].model !=3D model) { + continue; + } =20 - dev =3D isa_create(bus, "m48t59_isa"); - qdev_prop_set_uint32(&dev->qdev, "model", model); - qdev_prop_set_uint32(&dev->qdev, "size", size); - qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); - qdev_init_nofail(&dev->qdev); - d =3D DO_UPCAST(M48t59ISAState, busdev, dev); - s =3D &d->state; + dev =3D isa_create(bus, m48txx_info[i].isa_name); + qdev_init_nofail(&dev->qdev); + d =3D DO_UPCAST(M48t59ISAState, busdev, dev); + s =3D &d->state; =20 - return s; + return s; + } + + assert(false); + return NULL; } =20 static void m48t59_init_common(M48t59State *s) @@ -693,24 +746,32 @@ static void m48t59_init_common(M48t59State *s) =20 static int m48t59_init_isa1(ISADevice *dev) { + ISADeviceClass *ic =3D ISA_DEVICE_GET_CLASS(dev); + M48txxISADeviceClass *u =3D container_of(ic, M48txxISADeviceClass, + parent_class); M48t59ISAState *d =3D DO_UPCAST(M48t59ISAState, busdev, dev); M48t59State *s =3D &d->state; =20 + s->model =3D u->info.model; + s->size =3D u->info.size; isa_init_irq(dev, &s->IRQ, 8); m48t59_init_common(s); memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); - if (s->io_base !=3D 0) { - isa_register_ioport(dev, &d->io, s->io_base); - } + isa_register_ioport(dev, &d->io, 0x74); =20 return 0; } =20 static int m48t59_init1(SysBusDevice *dev) { + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_GET_CLASS(dev); + M48txxSysBusDeviceClass *u =3D container_of(k, M48txxSysBusDeviceCla= ss, + parent_class); M48t59SysBusState *d =3D FROM_SYSBUS(M48t59SysBusState, dev); M48t59State *s =3D &d->state; =20 + s->model =3D u->info.model; + s->size =3D u->info.size; sysbus_init_irq(dev, &s->IRQ); =20 memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->s= ize); @@ -720,58 +781,62 @@ static int m48t59_init1(SysBusDevice *dev) return 0; } =20 -static Property m48t59_isa_properties[] =3D { - DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), - DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), - DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), - DEFINE_PROP_END_OF_LIST(), -}; - -static void m48t59_init_class_isa1(ObjectClass *klass, void *data) +static void m48t59_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ISADeviceClass *ic =3D ISA_DEVICE_CLASS(klass); + M48txxISADeviceClass *u =3D container_of(ic, M48txxISADeviceClass, + parent_class); + M48txxInfo *info =3D data; + ic->init =3D m48t59_init_isa1; dc->no_user =3D 1; dc->reset =3D m48t59_reset_isa; - dc->props =3D m48t59_isa_properties; + u->info =3D *info; } =20 -static const TypeInfo m48t59_isa_info =3D { - .name =3D "m48t59_isa", - .parent =3D TYPE_ISA_DEVICE, - .instance_size =3D sizeof(M48t59ISAState), - .class_init =3D m48t59_init_class_isa1, -}; - -static Property m48t59_properties[] =3D { - DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), - DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), - DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void m48t59_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + M48txxSysBusDeviceClass *u =3D container_of(k, M48txxSysBusDeviceCla= ss, + parent_class); + M48txxInfo *info =3D data; =20 k->init =3D m48t59_init1; dc->reset =3D m48t59_reset_sysbus; - dc->props =3D m48t59_properties; + u->info =3D *info; } =20 -static const TypeInfo m48t59_info =3D { - .name =3D "m48t59", - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(M48t59SysBusState), - .class_init =3D m48t59_class_init, -}; - static void m48t59_register_types(void) { - type_register_static(&m48t59_info); - type_register_static(&m48t59_isa_info); + TypeInfo m48txx_type_info =3D { + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(M48t59SysBusState), + .class_size =3D sizeof(M48txxSysBusDeviceClass), + .class_init =3D m48t59_class_init, + }; + TypeInfo m48txx_isa_type_info =3D { + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(M48t59ISAState), + .class_size =3D sizeof(M48txxISADeviceClass), + .class_init =3D m48t59_isa_class_init, + }; + int i; + + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (m48txx_info[i].sysbus_name) { + m48txx_type_info.name =3D m48txx_info[i].sysbus_name; + m48txx_type_info.class_data =3D &m48txx_info[i]; + type_register(&m48txx_type_info); + } + + if (m48txx_info[i].isa_name) { + m48txx_isa_type_info.name =3D m48txx_info[i].isa_name; + m48txx_isa_type_info.class_data =3D &m48txx_info[i]; + type_register(&m48txx_isa_type_info); + } + } } =20 type_init(m48t59_register_types) --=20 1.7.10.4