From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chad Versace Subject: [PATCH] intel: Add pci id for Haswell Harris Beach Mobile GT2+ Date: Mon, 15 Apr 2013 17:52:10 -0700 Message-ID: <1366073530-12098-1-git-send-email-chad.versace@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 848CBE5F7E for ; Mon, 15 Apr 2013 17:52:13 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Signed-off-by: Chad Versace --- intel/intel_chipset.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index b73fa0f..da2fbee 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -82,6 +82,7 @@ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_HASWELL_HSB_M_GT2_PLUS 0x0A26 /* Mobile */ #define IS_830(dev) (dev == 0x3577) #define IS_845(dev) (dev == 0x2562) @@ -198,7 +199,8 @@ devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ - devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) + devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_HSB_M_GT2_PLUS) #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ IS_HSW_GT2(devid)) -- 1.8.1.4