Re: [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend

[Imre Deak <imre.deak@intel.com>]

On Wed, 2013-04-17 at 16:05 -0300, Paulo Zanoni wrote:
> Hi
> 
> 2013/4/17 Imre Deak <imre.deak@intel.com>:
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > v2:
> > - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> > - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
> >
> 
> s/Paolo/Paulo/ :)

Ok, sorry..

> Besides this, the patch looks fine. But I can't test it right now
> since suspend seems to be broken on my machine, even with nomodeset.
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Yes, same here suspend is broken even without loading i915.

> 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c      |    2 ++
> >  drivers/gpu/drm/i915/i915_drv.h      |    1 +
> >  drivers/gpu/drm/i915/intel_display.c |    5 +++++
> >  drivers/gpu/drm/i915/intel_drv.h     |    1 +
> >  drivers/gpu/drm/i915/intel_pm.c      |   18 ++++++++++++++++++
> >  5 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 9ebe895..6902219 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> >                  */
> >                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> >                         dev_priv->display.crtc_disable(crtc);
> > +
> > +               intel_modeset_suspend_hw(dev);
> >         }
> >
> >         i915_save_state(dev);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b5a495a..e549e6c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
> >
> >  /* modesetting */
> >  extern void intel_modeset_init_hw(struct drm_device *dev);
> > +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> >  extern void intel_modeset_init(struct drm_device *dev);
> >  extern void intel_modeset_gem_init(struct drm_device *dev);
> >  extern void intel_modeset_cleanup(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index dce643c..dec9019 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> >         mutex_unlock(&dev->struct_mutex);
> >  }
> >
> > +void intel_modeset_suspend_hw(struct drm_device *dev)
> > +{
> > +       intel_suspend_hw(dev);
> > +}
> > +
> >  void intel_modeset_init(struct drm_device *dev)
> >  {
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index a124e05..3f31b2e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> >  #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> >
> >  extern void intel_init_clock_gating(struct drm_device *dev);
> > +extern void intel_suspend_hw(struct drm_device *dev);
> >  extern void intel_write_eld(struct drm_encoder *encoder,
> >                             struct drm_display_mode *mode);
> >  extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f747cb0..8a163d4 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> >                            PCH_LP_PARTITION_LEVEL_DISABLE);
> >  }
> >
> > +static void lpt_suspend_hw(struct drm_device *dev)
> > +{
> > +       struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +       if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> > +               uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> > +
> > +               val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> > +               I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> > +       }
> > +}
> > +
> >  static void haswell_init_clock_gating(struct drm_device *dev)
> >  {
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> >         dev_priv->display.init_clock_gating(dev);
> >  }
> >
> > +void intel_suspend_hw(struct drm_device *dev)
> > +{
> > +       if (HAS_PCH_LPT(dev))
> > +               lpt_suspend_hw(dev);
> > +}
> > +
> >  /**
> >   * We should only use the power well if we explicitly asked the hardware to
> >   * enable it, so check if it's enabled and also check if we've requested it to
> > --
> > 1.7.10.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> --
> Paulo Zanoni